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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ej-Araby, E. Gonzalez, I. El-Ghazawi, T. |
| Copyright Year | 2007 |
| Description | Author affiliation: George Washington Univ., Washington (Ej-Araby, E.; Gonzalez, I.; El-Ghazawi, T.) |
| Abstract | Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and/or floating-point computations. Exact computation, based on arbitrary-precision arithmetic, has been developed over the last decade as an emerging numerical computation paradigm in response to this problem of numerical non-robustness. Exact arithmetic, specifically arbitrary-precision arithmetic, has been traditionally implemented using efficient software libraries such as GNU multi-precision (GMP). However, this results in a slower arithmetic performance when compared to fixed-precision arithmetic. In this paper we present a first effort, to the best of our knowledge, of reconfigurable hardware support for arbitrary-precision arithmetic. The proposed hardware architectures are based on virtual convolution scheduling which is derived from a formal representation of the problem. Targeting high performance and efficiency, dynamic (non-linear) pipelines techniques were exploited to eliminate the effects of deeply-pipelined operators. Referenced to GMP, our experiments showed promising results. |
| Starting Page | 79 |
| Ending Page | 85 |
| File Size | 2004738 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424410590 |
| DOI | 10.1109/FPL.2007.4380629 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-08-27 |
| Publisher Place | Netherlands |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Digital arithmetic Floating-point arithmetic Computer languages Scientific computing Software libraries Computer architecture Convolution Pipelines High performance computing |
| Content Type | Text |
| Resource Type | Article |
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