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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Katashita ,. T. Maeda, A. Toda, K. Yamaguchi, Y. |
| Copyright Year | 2006 |
| Description | Author affiliation: National Inst. of Adv. Ind. Sci. & Technol., Tsukuba (Katashita , T.; Maeda, A.; Toda, K.; Yamaguchi, Y.) |
| Abstract | This paper proposes a method of generating a lightweight scalable NFA-based string matching circuit with elimination of redundant resources. String matching circuits have been studied extensively for intrusion detection systems. An NFA-based string matching circuit, one of the works, has expandability of the processing data width. Due to the huge hardware requirement, it was difficult to implement an NFA-based string matching circuit with the whole Snort 2.3.3 rule (35461 characters) that processes at 10 Gbps on a single FPGA. To reduce the circuit area, we eliminate redundant states of the NFA with the Aho-Corasick approach and redundant AND-gates in the NFA. Consequently, our method reduces the resource requirements by over 50% as compared with previous NFA-based circuits, and the synthesis result shows that a matching circuit that includes the whole Snort 2.3.3 rule can be implemented onto a single Xilinx Virtex-II pro xc2vp-100 with throughput over 10 Gbps |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 4208833 |
| Page Count | 4 |
| File Format | |
| ISBN | 142440312X |
| DOI | 10.1109/FPL.2006.311317 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-08-28 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Intrusion detection Throughput Field programmable gate arrays Clocks Circuit synthesis Data processing Electronics industry Industrial electronics Hardware Network synthesis |
| Content Type | Text |
| Resource Type | Article |
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