NDLI: Placement and Timing for FPGAs Considering Variations

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Table of contents

FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges

Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions

Academia to IPO - A Modern Odyssey

FPGA Architecture Design Methodology

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications

Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations

High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD

Placement and Timing for FPGAs Considering Variations

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations

Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays

System Level Architecture Exploration for Reconfigurable Systems On Chip

RAID 6 Hardware Acceleration

Detection Module in a Complementary Set of Sequences-Based Pulse Compression System

FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor

Activity Estimation for Field-Programmable Gate Arrays

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays

A Thermal Management and Profiling Method for Reconfigurable Hardware Applications

Modular Partitioning for Incremental Compilation

Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description

Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information

Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor

FPGA Vendor Agnostic True Random Number Generator

A Scalable Architecture for RSA Cryptography on Large FPGAs

Applying Partial Reconfiguration to Networks-On-Chips

On-FPGA Communication Architectures and Design Factors

Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture

OSSS+R: Modelling and Simulating Self-Reconfigurable Systems

A Simulation Platform for Reconfigurable Computing Research

Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems

FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex

An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic

Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor

Multitasking Support for Dynamically Reconfig Urable Systems

An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems

Non-Uniform Random Number Generation Through Piecewise Linear Approximations

Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models

Fast Emulation of Permanent Faults in VLSI Systems

Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem

The Entropy of FPGA Reconfiguration

Adaptive FPGAs: High-Level Architecture and a Synthesis Method

Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics

Mapping Recursive Functions to Reconfigurable Hardware

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor

An FPGA Solver for Large SAT Problems

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor

Ray Tracing Hardware System Using Plane-Sphere Intersections

Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs

Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming

On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware

Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support

Executing Hardware as Parallel Software for Picoblaze Networks

High-Performance and Parameterized Matrix Factorization on FPGAs

On Reconfigurable Architectures for Efficient Matrix Inversion

FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach

Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm

Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique

Variable-Length Hashing for Exact Pattern Matching

High Speed Document Clustering in Reconfigurable Hardware

Regular Expression Software Deceleration for Intrusion Detection Systems

FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems

A Reconfigurable Viterbi Decoder for a Communication Platform

Intelligent Parking System Design Using FPGA

Adaptive Optics Real-Time Control Using FPGA

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs

Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells

Defect-Tolerant FPGA Architecture Exploration

Automation of IP Core Interface Generation for Reconfigurable Computing

Identifying FPGA IP-Cores Based on Lookup Table Content Analysis

IPP Watermarking Technique for IP Core Protection on FPL Devices

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV

Real-Time Video Pixel Matching

Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design

Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures

Minimizing Communication Cost for Reconfigurable Slot Modules

Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions

A Layer Model for Systematically Designing Dynamically Reconfigurable Systems

Efficient Realtime FPGA Implementation of the Trace Transform

Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA

An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree

A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors

A Multi-Context Pipelined Array for Embedded Systems

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures

Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed

Multi-layer Floorplanning on a Sequence of Reconfigurable Designs

Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding

A Flexible Implementation of a Temporal Filter with Motion Compensation

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime

A Dynamic Reconfigurable Fabric for Platform SoCs

FPGA Implementation of 3-D Thermal Model Simulator

Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration

Using Reconfigurable HW for High Dimensional CAF Computation

FPGA-Based Boundary-Scan Bist

A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access

Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm

Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools

FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation

Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation

A Congestion Driven Placement Algorithm for FPGA Synthesis

An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor

An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution

FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences

A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup

An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures

An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion

Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Skin Color Detection for Real Time Mobile Applications

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem

Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation

A Compiler Intermediate Representation for Reconfigurable Fabrics

A Segmentation Model for Partial Run-Time Reconfiguration

On Feasibility of FPGA Bitstream Compression During Placement and Routing

Sizing of Processing Arrays for FPGA-Based Computation

Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices

Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver

Multi Stream Cipher Architecture for Reconfigurable System-on-Chip

Astra: An Advanced Space-Time Reconfigurable Architecture

Self-Reconfigurable Pervasive Platform for Cryptographic Application

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor

Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching

FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip

A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection

A-B Nodes Classification for Power Estimation

Area-Efficient Implementation of a Pulse-Mode Neuron Model

Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators

Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures

An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot

A Codesign Tool for High Level Systhesis of Vision Models on FPL

On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips

FPGA Implementation of High-Performance PHM / DPHM Schedulers

Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip

A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes

Reconfigurable Systems Enabled by a Network-on-Chip

Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture

Execution Objects for Dynamically Reconfigurable FPGA Systems

A Dynamically Reconfigurable Queue Scheduler

General Digit Width Normal Basis Multipliers with Circular and Linear Structure

FPGA Based Imaging Particle Detector Trigger System

A Leak Resistant Architecture Against Side Channel Attacks

Hthreads: A Computational Model for Reconfigurable Devices

Efficient Cell Designs for Systolic Smith-Waterman Implementations

FPGA Implementation and Power Modelling of the Fast Walsh Transform

A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture Discrimination

Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors

High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures

Predictive Load Balancing for Interconnected FPGAs

The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory

Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip

Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks

Investigating Trace Transform Architectures for Face Authentication

Configware Design Space Exploration Using Rewriting Logic

Dynamic Memory Sub-System for Reconfigurable Platforms

A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment

Evaluation and Design of Processor-Like Reconfigurable Architectures

Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic

A Dual Cache for Performance and Energy Aware Reconfigurable HW

Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign

Can Graphics Processing Units be Used to Improve Video Processing Systems?

Architecture and CAD for FPGA Clock Networks

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs

High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing

FPGA Based Architectures for H. 264/AVC Video Compression Standard

Power Optimization Techniques for SRAM-Based FPGAs

Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling

An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization

A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment

International Conference on Field Programmable Logic and Applications, 2005.

Placement and Timing for FPGAs Considering Variations

Content Provider	IEEE Xplore Digital Library
Author	Yan Lin Hutton, M. Lei He
Copyright Year	2006
Description	Author affiliation: UCLA, Los Angeles (Yan Lin; Lei He)
Abstract	Process variation affecting timing and power is an important issue for modern integrated circuits in nanometer technologies. FPGAs are similar to ASICs in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. This paper presents the first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs. Considering the uniqueness of reprogrammability in FPGAs, we quantify the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield. We also develop a new variation aware placement, which is the first statistical algorithm for FPGA layout and reduces yield loss by 3.4x with guard-banding and 25x with speed-binning for MCNC and QUIP designs.
Starting Page	1
Ending Page	7
File Size	6475811
Page Count	7
File Format	PDF
ISBN	142440312X
DOI	10.1109/FPL.2006.311192
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-28
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Field programmable gate arrays Delay estimation Helium Modems Clocks Frequency Routing Integrated circuit technology Circuit testing
Content Type	Text
Resource Type	Article

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