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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Carroll, A. Ebeling, C. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA (Carroll, A.; Ebeling, C.) |
| Abstract | Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to address this problem, where long distance routes are pipelined using registers available in the configurable interconnect architecture. Unfortunately, pipelined interconnects are much harder to route than simple interconnects. QuickRoute is a fast, heuristic router based on PathFinder for pipelined interconnects. While its performance scales well with circuit size, it requires $O(N^{2})$ space and in practice can only be used for circuits with up to about 10,000 nodes. This paper describes an efficient solution to this space problem based on arithmetic coding, a technique widely used in data compression. We show that this reduces the space complexity to O(NlogN) while only slightly affecting performance. This result will allow pipelined routing to be used even for very large FPGA architectures. Experiments show that memory usage is reduced by 90% even for our relatively small coarse-grained benchmark circuits |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 139676 |
| Page Count | 6 |
| File Format | |
| ISBN | 142440312X |
| DOI | 10.1109/FPL.2006.311274 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-08-28 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Encoding Integrated circuit interconnections Delay Field programmable gate arrays Registers Pipeline processing Logic arrays Computer architecture Computer science |
| Content Type | Text |
| Resource Type | Article |
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