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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Malik, U. Diessel, O. |
| Copyright Year | 2006 |
| Description | Author affiliation: Sch. of Comput. Sci. & Eng.,, New South Wales Univ., Sydney, NSW (Malik, U.; Diessel, O.) |
| Abstract | In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 1-10% of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 125982 |
| Page Count | 6 |
| File Format | |
| ISBN | 142440312X |
| DOI | 10.1109/FPL.2006.311223 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-08-28 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Entropy Field programmable gate arrays Circuits Hardware Clocks Australia Council Computer science Real time systems Operating systems Acceleration |
| Content Type | Text |
| Resource Type | Article |
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