NDLI: 100 Gbit/s Fully Integrated InP DHBT-Based CDR/1:2 DEMUX IC

Content Provider	IEEE Xplore Digital Library
Author	Makon, R.E. Driad, R. Losch, R. Rosenzweig, J. Schlechtweg, M.
Copyright Year	2008
Description	Author affiliation: Fraunhofer Inst. for Appl. Solid State Phys. (IAF), Freiburg (Makon, R.E.; Driad, R.; Losch, R.; Rosenzweig, J.; Schlechtweg, M.)
Abstract	In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The integrated circuit (IC) is realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both $f_{T}$ and $f_{max}.$ The CDR IC consists mainly of a half-rate linear phase detector including a 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). A 100 Gbit/s data signal at the corresponding input of the CDR circuit gives rise to 50 Gbit/s recovered and demultiplexed output data featuring clear eye opening and a voltage swing of 500 $mV_{pp}.$ The extracted 50 GHz clock signal from the input data features a voltage swing of 250 $mV_{pp},$ while the corresponding peak-to-peak (pp) and rms jitter amount to 2.1 ps and 0.5 ps, respectively. The full IC dissipates 2.1 W at a single supply voltage of -4.5 V.
Starting Page	1
Ending Page	4
File Size	586163
Page Count	4
File Format	PDF
ISBN	9781424419395
ISSN	15508781
DOI	10.1109/CSICS.2008.36
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Indium phosphide Voltage DH-HEMTs Clocks Bipolar integrated circuits Voltage-controlled oscillators Bipolar transistors Integrated circuit technology Cutoff frequency Phase detection
Content Type	Text
Resource Type	Article

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