NDLI: A ultra-low-power sensor signal processor for high-performance close-loop MEMS accelerometer

Content Provider	IEEE Xplore Digital Library
Author	Chao Wang Jingjing Lan Jianwen Luo Nag, D. Chai, K.T.C. Grinberg, B.
Copyright Year	2015
Description	Author affiliation: Inst. of Microelectron., A*STAR, Singapore, Singapore (Chao Wang; Jingjing Lan; Jianwen Luo; Nag, D.; Chai, K.T.C.) \|\| Phys. Logic, Israel (Grinberg, B.)
Abstract	This paper presents an Micro-Controller Unit (MCU) based ultra-low-power sensor signal processor design for a close-loop capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometer. The proposed sensor signal processor provides basic sensor micro-system control and advanced signal processing functions, including analogue front-end configuration, digital delta-sigma modulation and decimation filtering. The accelerator design of the digital delta-sigma modulator offers good flexibility and re-configurability to enable a close-loop MEMS accelerometer with a wide dynamic range of up to 109 dB and a low nonlinearity of 0.01% from the system-level simulation. By applying ultra-low-power techniques including clock gating, power gating and ultra-low-voltage operation, a power reduction by two orders of magnitude is achieved as compared to original design in 0.18-μm CMOS technology. Simulation result shows that the digital sensor signal processing core only consumes 25.3 μW at 0.6 V in ultra low power mode.
Starting Page	91
Ending Page	94
File Size	274262
Page Count	4
File Format	PDF
ISBN	9781479983629
e-ISBN	9781479983643
DOI	10.1109/EDSSC.2015.7285057
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-01
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	close loop Ultra low lower sensor node processor accelerometer MEMS
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in