NDLI: Whitespace-aware TSV arrangement in 3D clock tree synthesis

Content Provider	IEEE Xplore Digital Library
Author	Xin Li Wulong Liu Haixiao Du Yu Wang Yuchun Ma Huazhong Yang
Copyright Year	2013
Description	Author affiliation: EE Dept., Tsinghua Univ., Beijing, China (Xin Li; Wulong Liu; Haixiao Du; Yu Wang; Yuchun Ma; Huazhong Yang)
Abstract	Through-silicon via (TSV) could provide vertical connections between different dies in three-dimensional integrated circuits (3D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3D clock tree synthesis (CTS) because only few whitespace blocks can be used for clock TSVs after floorplan and placement. Unlike most of the published previous works that ignore whitespace, this paper for the first time proposes a whitespace-aware TSV arrangement algorithm in 3D CTS. The algorithm consists of three stages: sink pre-clustering, whitespace-aware three-dimensional method of means and medians (3D-MMM) topology generation and deferred-merge embedding (DME) merging segment reconstruction. We also present a TSV whitespace-aware 3D CTS flow. Experiment results show that our proposed algorithm is more practical and efficient, the average skew and power can be reduced by 49.2% and 1.9% respectively, compared to the traditional 3D-MMM based CTS method with TSV moving adjustment.
Starting Page	115
Ending Page	120
File Size	1264139
Page Count	6
File Format	PDF
ISBN	9781479913312
ISSN	21593469
DOI	10.1109/ISVLSI.2013.6654632
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-05
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Clocks Three-dimensional displays Merging Algorithm design and analysis Topology Routing TSV arrangement Clock tree synthesis 3D ICs Whitespace
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis

TSV-aware topology generation for 3D Clock Tree Synthesis

Gated low-power clock tree synthesis for 3D-ICs

Efficient region-aware P/G TSV planning for 3D ICs

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

Thermal aware clock tree optimization with balanced clock skew in 3D ICs

TSV-aware analytical placement for 3D IC designs

Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs

Whitespace-aware TSV arrangement in 3D clock tree synthesis

Similar Documents

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis

TSV-aware topology generation for 3D Clock Tree Synthesis

Gated low-power clock tree synthesis for 3D-ICs

Efficient region-aware P/G TSV planning for 3D ICs

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

Thermal aware clock tree optimization with balanced clock skew in 3D ICs

TSV-aware analytical placement for 3D IC designs

Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs

Whitespace-aware TSV arrangement in 3D clock tree synthesis