NDLI: Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder

Content Provider	IEEE Xplore Digital Library
Author	da Silva, T.L. Vortmann, J.A. Agostini, L.V. Susin, A.A. Bampi, S.
Copyright Year	2009
Abstract	This paper presents a low cost and memoryless hardware design for the Context Adaptive Variable Length Decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD symbols in H.264/AVC since a great number of syntax elements are decoded based on look-up tables. This is an important problem given the high hardware cost and the high power dissipation caused by the large number of memory accesses. Thus, to solve this problem, we designed an efficient decoding of syntax elements using tree structures. The architecture designed was described in VHDL and synthesized to Altera Stratix II FPGA and to TSMC 0.18μm standard-cells technologies. The results obtained show that our architecture has significant savings in hardware resources consumption and in the number of memory accesses in comparison to other published works. Our design reached the necessary throughput to decode SDTV videos (720x576 pixels) in real-time.
Starting Page	280
Ending Page	285
File Size	614694
Page Count	6
File Format	PDF
ISBN	9781424444083
DOI	10.1109/ISVLSI.2009.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Memory architecture Automatic voltage control Decoding Hardware Video coding Power dissipation Tree data structures Field programmable gate arrays Throughput Architectural Design Video compression CAVLD H.264/AVC standard
Content Type	Text
Resource Type	Article

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