NDLI: A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching

Content Provider	IEEE Xplore Digital Library
Author	Jian Huang Jooheung Lee
Copyright Year	2009
Abstract	In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different number of DCT coefficients in the zig-zag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose a configuration manager which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use LZSS algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve 400 MBytes/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration.
Starting Page	67
Ending Page	72
File Size	186362
Page Count	6
File Format	PDF
ISBN	9781424444083
DOI	10.1109/ISVLSI.2009.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Prefetching Field programmable gate arrays Computer architecture Runtime Hardware Power engineering computing Throughput Video coding Quantization FPGA DCT dynamic partial reconfiguration self reconfigurable compression
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching

An Efficient Reconfigurable Image Compression Architecture

FPGA partitioning and synthesis of reconfigurable video compression module

Image compression on FPGA using DCT

An FPGA-based video compressor for H.263 compatible bitstreams

High throughput pipelined 2D Discrete cosine transform for video compression

Implementation of DCT for video compression with reconfigurable technology

FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications

Implementation of two dimensional forward DCT and inverse DCT using FPGA

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching

Similar Documents

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching

An Efficient Reconfigurable Image Compression Architecture

FPGA partitioning and synthesis of reconfigurable video compression module

Image compression on FPGA using DCT

An FPGA-based video compressor for H.263 compatible bitstreams

High throughput pipelined 2D Discrete cosine transform for video compression

Implementation of DCT for video compression with reconfigurable technology

FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications

Implementation of two dimensional forward DCT and inverse DCT using FPGA

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching