NDLI: High Speed Parallel Architecture for Cyclic Convolution Based on FNT

Content Provider	IEEE Xplore Digital Library
Author	Jian Zhang Shuguo Li
Copyright Year	2009
Abstract	This paper presents a high speed parallel architecture for cyclic convolution based on Fermat Number Transform (FNT) in the diminished-1 number system. A code conversion method without addition (CCWA) and a butterfly operation method without addition (BOWA) are proposed to perform the FNT and its inverse (IFNT) except their final stages in the convolution. The pointwise multiplication in the convolution is accomplished by modulo 2n+1 partial product multipliers (MPPM) and output partial products which are inputs to the IFNT. Thus modulo 2n+1 carry propagation additions are avoided in the FNT and the IFNT except their final stages and the modulo 2n+1 multiplier. The execution delay of the parallel architecture is reduced evidently due to the decrease of modulo 2n+1 carry-propagation addition. Compared with the existing cyclic convolution architecture, the proposed one has better throughput performance and involves less hardware complexity. Synthesis results using 130nm CMOS technology demonstrate the superiority of the proposed architecture over the reported solution.
Starting Page	199
Ending Page	204
File Size	292982
Page Count	6
File Format	PDF
ISBN	9781424444083
DOI	10.1109/ISVLSI.2009.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel architectures Convolution Delay Hardware CMOS technology Arithmetic Computer Society Very large scale integration Microelectronics Throughput butterfly operation cyclic convolution Fermat number transform code conversion
Content Type	Text
Resource Type	Article

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