NDLI: Leakage power driven behavioral synthesis of pipelined datapaths

Content Provider	IEEE Xplore Digital Library
Author	Gopalan, R. Gopalakrishnan, C. Katkoori, S.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA (Gopalan, R.; Gopalakrishnan, C.; Katkoori, S.)
Abstract	We present a scheduling, allocation and binding methodology that employs MTCMOS as the standby leakage reduction mechanism. We use the simulated annealing meta-heuristic for optimizing leakage power The cost functions for our approach are obtained after extensive characterization trials taking into account, the run-time characteristics of the MTCMOS approach. Our approach makes use of two cost factors: leakage cost, for optimizing the number of MTCMOS instances, and settling cost, for the minimization of their active-to-standby transitions. We enhance throughput and performance of the datapaths by synthesizing them as functionally pipelined systems before performing our optimizations. Using fully pre-characterized leakage libraries for RT-level simulation, we obtain an average leakage power reduction of 36.2%, and an average area overhead of 6.2%. However, with a small increase in schedule latency, we obtain an average reduction of around 3.95%-4.6% in the total area.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	167
Ending Page	172
File Size	143267
Page Count	6
File Format	PDF
ISBN	076952365X
DOI	10.1109/ISVLSI.2005.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Cost function Delay Power dissipation Runtime Very large scale integration Computer science Power engineering and energy Processor scheduling Computational modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Tabu search based behavioural synthesis of low leakage datapaths

Low-power binding of function units in high-level synthesis

An efficient low-power binding algorithm in high-level synthesis

A Pipelined 330 MHz Multiplier

A cycle-accurate compilation algorithm for custom pipelined datapaths

Digit pipelined discrete wavelet transform

Static Power Reduction Techniques for Asynchronous Circuits

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

A scheduling and partitioning scheme for low power circuit operating at multiple voltages

Leakage power driven behavioral synthesis of pipelined datapaths

Similar Documents

Tabu search based behavioural synthesis of low leakage datapaths

Low-power binding of function units in high-level synthesis

An efficient low-power binding algorithm in high-level synthesis

A Pipelined 330 MHz Multiplier

A cycle-accurate compilation algorithm for custom pipelined datapaths

Digit pipelined discrete wavelet transform

Static Power Reduction Techniques for Asynchronous Circuits

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

A scheduling and partitioning scheme for low power circuit operating at multiple voltages

Leakage power driven behavioral synthesis of pipelined datapaths