NDLI: Pipelined memory controllers for DSP applications handling unpredictable data accesses

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

Pipelined memory controllers for DSP applications handling unpredictable data accesses

Content Provider	IEEE Xplore Digital Library
Author	Le Gal, B. Casseau, E. Huet, S. Martin, E.
Copyright Year	2005
Description	Author affiliation: LESTER Lab., South Brittany Univ., Lorient, France (Le Gal, B.; Casseau, E.; Huet, S.; Martin, E.)
Abstract	Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access controllers can be generated improving the pipeline access mode to RAM. We focus on the design and the implementation of memory sequencers that can be automatically generated from a behavioral synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	268
Ending Page	269
File Size	170438
Page Count	2
File Format	PDF
ISBN	076952365X
DOI	10.1109/ISVLSI.2005.56
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Random access memory Pipelines Computer architecture High level synthesis Timing Read-write memory Hazards Memory architecture Energy consumption
Content Type	Text
Resource Type	Article

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