NDLI: The use of pre-evaluation phase in dynamic CMOS logic

Content Provider	IEEE Xplore Digital Library
Author	Rao, A. Haniotakis, Th. Tsiatouhas, Y. Djemil, H.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA (Rao, A.; Haniotakis, Th.)
Abstract	Dynamic logic families have been shown to offer performance advantages over traditional CMOS logic. Their operation is based on the use of a clock signal that provides two operation phases: the precharge phase and evaluation phase. The precharge phase is setting the circuit at a predefined initial state while the actual logic response is determined during the evaluation phase. In this paper we examine potential advantages when an additional phase, called pre-evaluation, is introduced. During this phase a restricted voltage swing occurs depending on the desired outcome. This voltage swing is amplified during the final evaluation in order to produce the final logic response. By restricting the required voltage swing at internal logic nodes (especially in case of those presenting high capacitance) we are able to achieve higher performance coupled with reduced power consumption.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	270
Ending Page	271
File Size	59891
Page Count	2
File Format	PDF
ISBN	076952365X
DOI	10.1109/ISVLSI.2005.72
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits Voltage Logic circuits Clocks Logic design Capacitance Coupling circuits Energy consumption Very large scale integration Computer science Low Power Domino Pre-Evaluation
Content Type	Text
Resource Type	Article

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