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2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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1997 IEEE International Conference on Acoustics, Speech, and Signal Processing

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Digit pipelined discrete wavelet transform

Content Provider	IEEE Xplore Digital Library
Author	Nagendra, C. Irwin, M.J. Owens, R.M.
Copyright Year	1994
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA (Nagendra, C.; Irwin, M.J.; Owens, R.M.)
Abstract	The paper describes a digit pipelined architecture for the 1D discrete wavelet transform, assuming a digit-serial model of computation. The use of simple operations and data movement makes it suitable for VLSI implementation and it can be easily mapped onto fine-grain custom VLSI and FPGA-based architectures. It achieves a factor of two speedup over a previous implementation of the same algorithm by virtue of digit pipelining made possible by the use of signed-digit arithmetic. In addition, the system can be clocked faster since it uses only nearest neighbor connections on a mesh, thus avoiding the signal propagation delays associated with long routing paths. An N-point DWT takes O(Nk) time and requires O(LJk) area, where L is the filter size, J is the number of octaves and k is the precision.<>
File Size	346707
File Format	PDF
ISBN	0780317750
ISSN	15206149
DOI	10.1109/ICASSP.1994.389635
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-19
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Computer architecture Very large scale integration Computational modeling Pipeline processing Arithmetic Clocks Nearest neighbor searches Propagation delay Routing
Content Type	Text
Resource Type	Article

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