NDLI: New advances in path delay fault testing of combinational circuits

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New advances in path delay fault testing of combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Xie, X. Albicki, A.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Rochester Univ., NY, USA (Xie, X.; Albicki, A.)
Abstract	We show that not all path delay faults in a prime and irredundant two-level circuit need to be tested by robust tests in order to avoid test invalidation. This finding leads to a simplified testing procedure which guarantees 100% path delay fault testability. For the collapsible multi-level circuits, we introduce the concepts of m-primeness and m-irredundancy similar to the concepts used in two-level circuits. We prove that all path delay faults in a m-prime and m-irredundant multi-level circuit are virtually testable without testing invalidation. For the uncollapsible multi-level circuits, we propose a novel modular-based path delay fault model. Using this new model, the number of target path delay faults is substantially reduced.
Starting Page	272
Ending Page	277
File Size	649122
Page Count	6
File Format	PDF
ISBN	0818654406
DOI	10.1109/VTEST.1994.292301
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Combinational circuits Robustness Circuit synthesis Delay effects Registers Very large scale integration Fault diagnosis Polynomials
Content Type	Text
Resource Type	Article

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