NDLI: Design for testability of on-line multipliers

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Design for testability of on-line multipliers

Content Provider	IEEE Xplore Digital Library
Author	Bederr, H. Nicolaidis, M. Guyot, A.
Copyright Year	1994
Description	Author affiliation: TIMA/INPG, Grenoble, France (Bederr, H.; Nicolaidis, M.; Guyot, A.)
Abstract	This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controllability and observability of the different elements are very low. In particular, an embedded sequential array cannot be accessed directly and has no primary outputs. Therefore, we propose here two DFT alternatives. The first one determines the most significant nodes to be considered in order to avoid error masking. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. Both options have a low area overhead and a reduced number of extra pins.
Starting Page	408
Ending Page	414
File Size	760166
Page Count	7
File Format	PDF
ISBN	0818654406
DOI	10.1109/VTEST.1994.292281
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design for testability Circuit testing Observability Arithmetic Adders Controllability Parallel processing Concurrent computing Logic arrays Circuit faults
Content Type	Text
Resource Type	Article

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