NDLI: Program slicing for hierarchical test generation

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Program slicing for hierarchical test generation

Content Provider	IEEE Xplore Digital Library
Author	Vedula, V.M. Abraham, J.A. Bhadra, J.
Copyright Year	2002
Description	Author affiliation: Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA (Vedula, V.M.; Abraham, J.A.)
Abstract	Sequential Automatic Test Pattern Generation (ATPG) is extremely computation intensive and produces good results only on relatively small designs. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical ATPG which targets one module at a time and abstracts the rest of the design. The technique for obtaining a "constraint slice" for each embedded Module Under Test (MUT) within a design is described in detail. The technique has been incorporated in an automated tool for designs described in Verilog, and results on large benchmark circuits show the significant benefits of the approach.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	237
Ending Page	243
File Size	384184
Page Count	7
File Format	PDF
ISBN	0769515703
DOI	10.1109/VTS.2002.1011144
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Automatic test pattern generation Manufacturing Power engineering computing Circuit testing Very large scale integration Design for testability Test pattern generators Logic testing Application software
Content Type	Text
Resource Type	Article

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