NDLI: A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?

Content Provider	IEEE Xplore Digital Library
Author	Lee Song Patton, P. Radermacher, W.
Copyright Year	2002
Description	Author affiliation: Teradyne (Lee Song)
Abstract	Summary form only given, as follows. For many years, the semiconductor industry has been predicting the emergence of DFT tester market, enabled by increasing number of devices being designed with DFT methodologies such as scan and BIST. The search for low cost DFT tester solutions has resulted in the first ITRS roadmap for a DFT tester in 1999 and a major revision of this roadmap in 2001. While it is generally understood that a DFT tester can be used to limit the digital test performance envelope in production testing, some trends in the industry, such as increase in mixed signal SOC designs and multi GHz serial IO interfaces, may be pushing the industry toward more highly configurable and higher performance test solutions. The relative immaturity of analog mixed signal DFT, coupled with increasing proliferation of mixed signal SOC devices, may also prevent the wholesale industry-wide adoption of digital-only DFT testers. In addition, the emergence of novel fault models, beyond the traditional SSA model, to cover the emerging defects found in advanced silicon technologies have been noticeably lacking. Adding to the fire has been continuing discussion of the now famous $200/pin tester, which highlights the pressure faced by ATE companies in looking for a viable business model that can provide both high performance and low cost DFT testers at the same time. The result of this cloudiness in the industry has been relative slowness in the development of DFT testers by the ATE industry. However, the fact that adoption of DFT in devices is continuing leads us to believe that a DFT tester market will emerge eventually. The question is what kinds of DFT testers can best exploit the opportunities presented in this cloudy market. This is the second of two sessions that will explore various approaches in DFT tester development, features that may determine the success of DFT testers, and potential catalysts that may cause wide-scale industry adoption of DFT testers. This session explores whether successful DFT testers will just be next logical steps in ATE evolution instead of radical revolution expected by some in the industry.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	129
Ending Page	129
File Size	178772
Page Count	1
File Format	PDF
ISBN	0769515703
DOI	10.1109/VTS.2002.1011123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Design for testability Semiconductor device testing Costs Performance evaluation System testing Electronics industry Design methodology Built-in self-test Production
Content Type	Text
Resource Type	Article

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