NDLI: Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs

Content Provider	IEEE Xplore Digital Library
Author	Pandey, A.R. Patel, J.H.
Copyright Year	2002
Description	Author affiliation: Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA (Pandey, A.R.; Patel, J.H.)
Abstract	As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a technique based on the reconfiguration of scan chains to reduce test time and test data volume for Illinois Scan Architecture (ILS) based designs. This technique is presented with details of hardware implementation as well as the test generation and test application procedures. The reduction in test time and test data volume achieved using this technique is quite significant in most circuits.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	9
Ending Page	15
File Size	328287
Page Count	7
File Format	PDF
ISBN	0769515703
DOI	10.1109/VTS.2002.1011104
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Costs Integrated circuit testing Very large scale integration Semiconductor device testing Computer architecture Integrated circuit manufacture Clocks Hardware Automatic test pattern generation
Content Type	Text
Resource Type	Article

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