NDLI: High-level synthesis for orthogonal scan

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High-level synthesis for orthogonal scan

Content Provider	IEEE Xplore Digital Library
Author	Norwood, R.B. McCluskey, E.J.
Copyright Year	1997
Description	Author affiliation: Center for Reliable Comput., Stanford Univ., CA, USA (Norwood, R.B.)
Abstract	Scan paths are commonly used in digital design to improve the testability of sequential circuits since a full scan path provides complete controllability and observability for every bistable element. A traditional scan path is implemented after the circuit has been designed, with little regard to the actual circuit function. High-level synthesis can exploit knowledge of the circuit function to synthesize a scannable circuit that has less area overhead than a circuit that has scan inserted after synthesis. In this paper, we discuss how synthesis algorithms that target orthogonal scan can result in final designs that are fully scanned and have as little as one-third the overhead of a traditional scan path.
Starting Page	370
Ending Page	375
File Size	683849
Page Count	6
File Format	PDF
ISBN	0818678100
ISSN	10930167
DOI	10.1109/VTEST.1997.600308
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Circuit testing Circuit synthesis Logic Sequential analysis Sequential circuits Controllability Flip-flops Observability Algorithm design and analysis
Content Type	Text
Resource Type	Article

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