NDLI: Robust sequential fault testing of iterative logic arrays

Content Provider	IEEE Xplore Digital Library
Author	Gizopoulos, D. Psarakis, M. Paschalis, A.
Copyright Year	1997
Description	Author affiliation: Inst. of Inf. & Telecommum., NCSR Demokritos, Athens, Greece (Gizopoulos, D.)
Abstract	Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.
Starting Page	238
Ending Page	244
File Size	840741
Page Count	7
File Format	PDF
ISBN	0818678100
ISSN	10930167
DOI	10.1109/VTEST.1997.600280
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Logic arrays Robustness Sequential analysis CMOS logic circuits Fault detection CMOS technology Semiconductor device modeling Delay Benchmark testing
Content Type	Text
Resource Type	Article

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