NDLI: Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD

Content Provider	IEEE Xplore Digital Library
Author	Edmonds, M. Kent, T.J. Chang, M. Kachian, J. Droopad, R. Chagarov, E. Kummel, A.C.
Copyright Year	2015
Description	Author affiliation: Mater. Sci. & Eng. Dept., Univ. of California San Diego, La Jolla, CA, USA (Edmonds, M.; Kent, T.J.; Kummel, A.C.) \|\| Appl. Mater., Sunnyvale, CA, USA (Chang, M.; Kachian, J.) \|\| Ingram Sch. of Eng., Texas State Univ., San Marcos, TX, USA (Droopad, R.) \|\| Dept. of Chem. & Biochem., Univ. of California San Diego, La Jolla, CA, USA (Chagarov, E.)
Abstract	$In_{0.53}Ga_{0.47}As$ contains an intrinsically high electron mobility making it an attractive alternative semiconductor material for use in the channel region of MOSFET devices. The semiconductor/oxide interface can degrade device performance through interfacial roughness or formation of surface defects containing electronic trap states that act to pin the surface Fermi level. Tri-gate structured field effect transistors (finFETs) are currently being implemented into commercialized logic chips, making defect reduction and passivation of the semiconductor planar and sidewall crystallographic faces critical in order to create an ideal interface between the semiconductor and the gate oxide. For InGaAs(001) based finFETs to become potential for commercial implementation, in-situ III-V surface cleaning or defect passivation techniques must be compatible with both the InGaAs (001) and (110) surfaces. STM was employed to show air exposed InGaAs (001) and (110) samples can be restored to the cleanliness of MBE grown samples through atomic hydrogen dosing and thermal annealing. STM was also employed to characterize the in-situ self-limiting CVD of a silicon hydride control layer used to passivate the missing dimer defect unit cells of the arsenic rich InGaAs(001)-(2×4) surface. Surface defect densities are compared and quantified throughout several STM images following the surface cleaning and passivation techniques.
Starting Page	1
Ending Page	2
File Size	175887
Page Count	2
File Format	PDF
ISBN	9781479973750
DOI	10.1109/VLSI-TSA.2015.7117580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-27
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface cleaning Hydrogen Rough surfaces Surface roughness Annealing
Content Type	Text
Resource Type	Article

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