NDLI: Sacrificial Deuterium Passivation for Improved Interface Engineering in Gate Stack Processing

Content Provider	IEEE Xplore Digital Library
Author	Pap, A.E. Battistig, G. Ducso, C. Barsony, I. Kamaras, K. Nenyei, Z. Dietl, W. Kirchner, C.
Copyright Year	2007
Description	Author affiliation: Hungarian Acad. of Sci., Budapest (Pap, A.E.; Battistig, G.; Ducso, C.; Barsony, I.)
Abstract	The high reactivity of the free silicon surface and its consequence: the "omnipresent" native silicon oxide hinder the interface engineering in many processing steps of IC technology on the atomic level. Methods known to eliminate the native oxide need in most cases vacuum processing. They frequently deteriorate the atomic flatness of the silicon. Hydrogen passivation by a proper DHF (diluted HF) treatment removes the native silicon oxide without roughening the surface while simultaneously maintaining a "quasi oxide free" surface in a neutral or vacuum ambient for short time. Under such circumstances the last thermal desorption peak of hydrogen is activated at around 480-500degC where the free silicon surface suddenly becomes extremely reactive. In this study we show that deuterium passivation is a promising technology. Due to the fact that deuterium adsorbs more strongly on a Si surface than hydrogen even at room temperature, deuterium passivation does not need vacuum processing and it ensures a robust process flow.
Starting Page	57
Ending Page	63
File Size	1443261
Page Count	7
File Format	PDF
ISBN	9781424412273
DOI	10.1109/RTP.2007.4383819
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-02
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Deuterium Passivation Silicon Hydrogen Rough surfaces Surface roughness Surface treatment Hafnium Temperature Robustness
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A novel surface passivation process for HfO/sub 2/ Ge MOSFETs

Interface passivation by deuterium for nanoscale CMOS devices

Interface engineering for high-k/Ge gate stack

GaAs p- and n-MOS devices integrated with novel passivation (plasma nitridation and AlN-surface passivation) techniques and ALD-HfO2/TaN gate stack

Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD

Reaction of DI water and silicon and its effect on gate oxide integrity

The effect of release-etch processing on surface microstructure stiction

Ammonium Fluoride Anti-stiction Treatments For Polysilicon Microstructures

SOI wafer achieved by smart-cut process

Sacrificial Deuterium Passivation for Improved Interface Engineering in Gate Stack Processing

Similar Documents

A novel surface passivation process for HfO/sub 2/ Ge MOSFETs

Interface passivation by deuterium for nanoscale CMOS devices

Interface engineering for high-k/Ge gate stack

GaAs p- and n-MOS devices integrated with novel passivation (plasma nitridation and AlN-surface passivation) techniques and ALD-HfO2/TaN gate stack

Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD

Reaction of DI water and silicon and its effect on gate oxide integrity

The effect of release-etch processing on surface microstructure stiction

Ammonium Fluoride Anti-stiction Treatments For Polysilicon Microstructures

SOI wafer achieved by smart-cut process

Sacrificial Deuterium Passivation for Improved Interface Engineering in Gate Stack Processing