NDLI: Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS

Content Provider	IEEE Xplore Digital Library
Author	Nishikawa, M. Okabe, K. Ikeda, K. Tamura, N. Maekawa, H. Umeyama, M. Kurata, H. Kase, M. Hashimoto, K.
Copyright Year	2009
Description	Author affiliation: Fujitsu Microelectronics Ltd., 1500 Mizono, Tado-cho, Kuwana, Mie, 511-0192, Japan (Nishikawa, M.; Okabe, K.; Ikeda, K.; Tamura, N.; Maekawa, H.; Umeyama, M.; Kurata, H.; Kase, M.; Hashimoto, K.)
Abstract	We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/µm at Vd = 1.0 V and Ion = 1154 µA/µm was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 µA/µm for Ioff = 100 nA/µm at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective “dual” embedded stressor.
Starting Page	26
Ending Page	27
File Size	389967
Page Count	2
File Format	PDF
ISBN	9781424427840
ISSN	1930885X
DOI	10.1109/VTSA.2009.5159276
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-27
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Implants Solids Epitaxial growth MOSFETs Capacitive sensors Silicon Ion implantation Guidelines Stress control
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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