NDLI: A Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory with Optimized ONO Thickness

Content Provider	IEEE Xplore Digital Library
Author	Woei-Cherng Wu Tien-Sheng Chao Wu-Chin Peng Wen-Luh Yang Jer-Chyi Wang Jian-Hao Chen Ming-Wen Ma Chao-Sung Lai Tsung-Yu Yang Tzu-Ping Chen Chien-Hung Chen Chih-Hung Lin Hwi-Huang Chen Ko, J.
Copyright Year	2007
Description	Author affiliation: Nat. Chiao Tung Univ., Hsinchu (Woei-Cherng Wu; Tien-Sheng Chao)
Abstract	High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well $V_{th}$ distribution is also presented. High program/erase speed (10 us/5 ms) and low programming current (3.5 u/A) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
Starting Page	1
Ending Page	2
File Size	1506771
Page Count	2
File Format	PDF
ISBN	142440584X
ISSN	1524766X
DOI	10.1109/VTSA.2007.378896
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SONOS devices Flash memory Very large scale integration Chaos Physics Microelectronics Data mining P-n junctions Interface states MONOS devices
Content Type	Text
Resource Type	Article

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