NDLI: Fully integrated and functioned 44nm DRAM technology for 1GB DRAM

Content Provider	IEEE Xplore Digital Library
Author	Hyunjin Lee Dae-Young Kim Bong-Ho Choi Gyu-Seong Cho Sung-Woong Chung Wan-Soo Kim Myoung-Sik Chang Young-Sik Kim Junki Kim Tae-Kyun Kim Hyung-Hwan Kim Hae-Jung Lee Han-Sang Song Sung-Kye Park Jin-Woong Kim Sung-Joo Hong Sung-Wook Park
Copyright Year	2008
Description	Author affiliation: R&D Div., Hynix Semicond. Inc., Ichon (Hyunjin Lee; Dae-Young Kim; Bong-Ho Choi; Gyu-Seong Cho; Sung-Woong Chung; Wan-Soo Kim; Myoung-Sik Chang; Young-Sik Kim; Junki Kim; Tae-Kyun Kim; Hyung-Hwan Kim; Hae-Jung Lee; Han-Sang Song; Sung-Kye Park; Jin-Woong Kim; Sung-Joo Hong; Sung-Wook Park)
Abstract	44 nm feature sized $8F^{2}$ 1Gb DRAM is fully integrated and functioned for the first time with the smallest cell size of 0.015 $um^{2}.$ A novel cell-transistor structure and new DRAM process technologies are developed. In order to control the threshold voltage uniformity and body-bias sensitivity of saddle-fin cell-transistor, the channel doping profile and saddle-fin geometric dependency were analytically expressed with experimental data. The weak fin height dependency on $cell-V_{T}$ diminishes the burden of the saddle-fin patterning processes. And the low body-bias sensitivity of the saddle-fin cell-transistor leads wide tWR (write recovery time) margins. Cylinder-like MIM cell capacitor with ZAZ dielectric is exploited on cell capacitor. Copper implemented triple-metal layer and WN barrier-metal techniques were developed to decrease chip size.
Starting Page	86
Ending Page	87
File Size	655400
Page Count	2
File Format	PDF
ISBN	9781424418022
DOI	10.1109/VLSIT.2008.4588572
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Logic gates Sensitivity Tin Transistors Dielectrics Doping
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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