NDLI: Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices

Content Provider	IEEE Xplore Digital Library
Author	Ghani, T. Mistry, K. Packan, P. Armstrong, M. Thompson, S. Tyagi, S. Bohr, M.
Copyright Year	2001
Description	Author affiliation: Portland Technol. Dev., OR, USA (Ghani, T.)
Abstract	In this paper, we present for the first time an asymmetric source/drain extension (SDE) transistor structure which can achieve high I/sub DSAT/ at gate dimensions below 50 nm. We demonstrate that this structure alleviates the severe I/sub DSAT/ degradation reported in the literature for devices when gate to source/drain overlap dimensions are reduced to under 20 nm/side (Thomson et al, 1998). Sub-15 nm gate to source/drain overlap is mandatory for supporting gate dimensions below 50 nm (Ghani et al, 2000). Moreover, fabrication of this structure employs a standard process flow in which SDE regions are formed by ion implantation and a subsequent drive-in anneal. Fundamental principles of device operation of the asymmetric SDE transistor are presented followed by a description of the process flow and an in-depth analysis of electrical characteristics and associated trade-offs.
Starting Page	17
Ending Page	18
File Size	254413
Page Count	2
File Format	PDF
ISBN	4891140127
DOI	10.1109/VLSIT.2001.934925
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Japan Soc. Of Applied Phys.
Subject Keyword	Implants Degradation Fabrication MOSFET circuits MOS devices CMOS technology Ion implantation Annealing Electric variables Virtual colonoscopy
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

100 nm gate length high performance/low power CMOS transistor structure

CMOS device technology toward 50 nm region-performance and drain architecture

High performance sub-50 nm CMOS with advanced gate stack

Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation

26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structure

Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Gate-oxide degradation from source/drain (S/D) boron diffusion

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Characterization of HfSiON Gate Dielectric with TiN Gate on Multi-Gate MOSFET

Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices

Similar Documents

100 nm gate length high performance/low power CMOS transistor structure

CMOS device technology toward 50 nm region-performance and drain architecture

High performance sub-50 nm CMOS with advanced gate stack

Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation

26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structure

Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Gate-oxide degradation from source/drain (S/D) boron diffusion

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Characterization of HfSiON Gate Dielectric with TiN Gate on Multi-Gate MOSFET

Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices