NDLI: Input Referred Offset Reduction in Very High Speed Differential Receivers

Content Provider	IEEE Xplore Digital Library
Author	Chauhan, R. Selvam, M.
Copyright Year	2013
Description	Author affiliation: Texas Instrum. (India) Pvt Ltd., Bangalore, India (Chauhan, R.; Selvam, M.)
Abstract	This paper explains a circuit architecture to minimize the impact of IRO (Input Referred Offset) in Differential amplifier based Receivers. Such receivers are used on high speed interfaces, like DDRs and LVDS, as they provide better timing and ensure proper detection of small swing signals. However the mismatch between the differential input arms causes IRO which in turn causes duty cycle distortion and degrades the receiver timing. At very high speeds it becomes necessary to minimize the impact of IRO. The proposed IRO reduction circuit uses a Digital controller which measures and reduces the IRO using a binary code. The timing improvement provided by this circuit scheme is validated on Silicon in 28nm CMOS process.
Sponsorship	IEEE Comput. Soc.
Starting Page	115
Ending Page	119
File Size	318106
Page Count	5
File Format	PDF
ISBN	9781467346399
ISSN	10639667
DOI	10.1109/VLSID.2013.173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Receivers Calibration Timing Resistors Silicon Logic gates CMOS integrated circuits Comparator IRO CMOS I/Os
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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