NDLI: CASHIER: A Cache Energy Saving Technique for QoS Systems

Content Provider	IEEE Xplore Digital Library
Author	Mittal, S. Zhao Zhang Yanan Cao
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Mittal, S.; Zhao Zhang; Yanan Cao)
Abstract	With each CMOS technology generation, leakage energy has been increasing at an exponential rate and hence, managing the energy consumption of large, last-level caches is becoming a critical research issue in modern chip design. Saving cache energy in QoS systems is especially challenging, since, to avoid missing deadlines, a suitable balance needs to be made between energy saving and performance loss. We present CASHIER, a Cache Energy Saving Technique for Quality of Service Systems. Cashier uses dynamic profiling to estimate the memory subsystem energy and execution time of the program under multiple last level cache (LLC) configurations. It then reconfigures LLC to an energy efficient configuration with a view to meet the deadline. In QoS systems, allowed slack may be specified either as percentage of baseline execution time or as absolute slack and Cashier can work for both these cases. The experiments show the effectiveness of Cashier in saving cache energy. For example, for an L2 cache size of 2MB and 5% allowed-slack over baseline, the average saving in memory subsystem energy by using Cashier is 23.6%.
Sponsorship	IEEE Comput. Soc.
Starting Page	43
Ending Page	48
File Size	291482
Page Count	6
File Format	PDF
ISBN	9781467346399
ISSN	10639667
DOI	10.1109/VLSID.2013.160
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image color analysis Quality of service Color Energy consumption Logic gates Program processors Benchmark testing last level cache QoS systems cache leakage energy saving low power online profiling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration

FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration

Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Energy Efficient Last Level Caches via Last Read/Write Prediction

Reducing cache leakage energy for hybrid SPM-cache architectures

Cache capacity and its effects on power consumption for tiled chip multi-processors

Power gating with block migration in chip-multiprocessor last-level caches

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems

CASHIER: A Cache Energy Saving Technique for QoS Systems

Similar Documents

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration

FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration

Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors

An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

Energy Efficient Last Level Caches via Last Read/Write Prediction

Reducing cache leakage energy for hybrid SPM-cache architectures

Cache capacity and its effects on power consumption for tiled chip multi-processors

Power gating with block migration in chip-multiprocessor last-level caches

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems

CASHIER: A Cache Energy Saving Technique for QoS Systems