NDLI: Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Varma, B.S.C. Paul, K. Balakrishnan, M.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India (Varma, B.S.C.; Paul, K.; Balakrishnan, M.)
Abstract	Three dimensional Fast Fourier Transform (3D-FFT) is popularly used in many scientific applications in various domains like image processing, bioinformatics and molecular dynamics. Typically 3D-FFT computation takes significant part of the execution time of these applications. In order to speedup these applications, it becomes necessary to accelerate 3D-FFT computation. 3D-FFT can be accelerated using Field Programmable Gate Array (FPGA) based accelerators. But speedup always may not be possible as FPGAs run at slower clock frequency vis-a-vis processors and the resources available in an FPGA device might not be sufficient for the implementation of a sufficient number of copies of the processing elements to compensate for the loss of clock frequency. FPGAs with heterogeneous mix of coarse grained hard blocks along with programmable soft logic, can facilitate implementing a much larger number of processing elements and thus achieve much higher speedups. Modern FPGAs do consist of different heterogeneous hard embedded blocks (HEBs) like multipliers, DSP blocks and memory units. It is easy to predict that many more such hard blocks will be embedded into future FPGAs. The evaluation approach to identify and incorporate HEBs is complex as there are many parameters and constraints like area, granularity routing resources, etc. that need to be considered in an integrated manner to get an efficient implementation. In this paper we show acceleration of 3D-FFT using future fabrics incorporating HEBs. By using these fabrics we show speedups of upto 1900x for 2048 point FFT. We also present an evaluation methodology to design future FPGA fabrics incorporating accelerators as hard embedded blocks. This methodology will be useful for i selection of blocks to be embedded into the fabric and ii evaluating the performance gain that can be achieved by such an embedding.
Sponsorship	IEEE Comput. Soc.
Starting Page	92
Ending Page	97
File Size	382722
Page Count	6
File Format	PDF
ISBN	9781467346399
ISSN	10639667
DOI	10.1109/VLSID.2013.169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Acceleration Digital signal processing Random access memory Bandwidth Fabrics Clocks Hard Embedded Blocks FPGA FPGA based Acceleration 3D-FFT
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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