NDLI: 4 GHz 130nm Low Voltage PLL Based on Self Biased Technique

Content Provider	IEEE Xplore Digital Library
Author	Viswanathan, B. Nair, S.R.R. Viswam, V. Vettickatt, J.J. Kulanthaivelu, R. Chandran, L.S.
Copyright Year	2010
Abstract	This paper explores a PLL core design that can satisfy a wide range of high frequency serial data communication applications. There exist several high frequency serial data communication protocols that co-exist today. The PLL design requirements for all these clock frequencies separately call for enormous design effort in terms of time and cost. It is desired to design a PLL core which makes it possible to address a wide segment of clock frequency requirement. The PLL achieves this using single 1.2V supply, it doesn’t use any special mask layers and also doesn’t need a bandgap reference for its operation. This PLL is based on self-biased technique and achieves high process technology independence, fixed damping factor, fixed bandwidth to operating frequency range and input phase offset cancellation. Here the self biased PLL in 130nm CMOS technology achieves the frequency range of 400 MHz to 4GHz. The PLL core is designed to accept a wide range of input reference frequencies.
Starting Page	330
Ending Page	334
File Size	294342
Page Count	5
File Format	PDF
ISBN	9781424455416
ISSN	10639667
e-ISBN	9781424455423
DOI	10.1109/VLSI.Design.2010.21
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage Phase locked loops Frequency CMOS technology Data communication Clocks Protocols Costs Photonic band gap Damping
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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