NDLI: An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops

Content Provider	IEEE Xplore Digital Library
Author	Srinivasan, B. Chandratre, V.B.
Copyright Year	2010
Abstract	In this paper, an improved high resolution CMOS timing generator using array of digital delay lock loops is presented. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed Delay Lock Loops use novel start controlled Dual Phase and frequency Detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. The delay lock loop locks to both the leading and trailing clock edges as the start controlled dual phase and frequency detector along with charge pump convert the phase difference into voltage, which greatly reduces the timing jitter. In the start controlled dual phase and frequency detector, the start-controlled circuit is used to provide a precise output without the locking problem. The results show that the total delay time between the input and the output of the DLL (Delay Lock Loop) is one clock cycle and all of the delay cells provide precise output without false locking or harmonic locking. Test results show a timing jitter of less than 5 pS for the DLL circuit and has very low phase sensitivity errors. The timing generator implemented as an array of delay locked loops has exponentially reduced the locking time as well avoids false locking or harmonic locking. An experimental proto type was simulated using 0.35µ technology with a supply voltage of 3.3V.
Starting Page	335
Ending Page	338
File Size	326975
Page Count	4
File Format	PDF
ISBN	9781424455416
ISSN	10639667
e-ISBN	9781424455423
DOI	10.1109/VLSI.Design.2010.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tracking loops Phase detection Phase frequency detector Clocks Delay effects Charge pumps Timing jitter Circuit testing Voltage control Frequency conversion Delay Lock Loop
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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