NDLI: Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

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2015 IEEE International Reliability Physics Symposium

Keynote Address 1: “Transistors and reliability in the innovation era”

Keynote Address 2: “Hybrid memory cube: Achieving high performance and high reliability”

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Technical program comittee

Board of directors

2014 IRPS Paper Awards to be Recognized at 2015 IRPS [6 awards]

2015 IRPS Tutorial Program [21 abstracts]

2013 IRPS Paper Awards Recognized at 2014 IRPS [6 awards]

Circuits and products

Impact of electrode surface modulation on time-dependent dielectric breakdown

A critical analysis of sampling-based reconstruction methodology for dielectric breakdown systems (BEOL/MOL/FEOL)

Intrinsic reliability of local interconnects for N7 and beyond

Intrinsic mechanism of non-linearity in Weibull TDDB lifetime and its impact on lifetime prediction

Self-heating characterization of FinFET SOI devices using 2D time resolved emission measurements

Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states

Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism

Time-integrated photon emission as a function of temperature in 32 nm CMOS

Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets

Muons and thermal neutrons SEU characterization of 28nm UTBB FD-SOI and Bulk eSRAMs

Critical charge dependence of correlation of different neutron sources for soft error testing

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs

A case study of electromigration reliability: From design point to system operations

Mechanisms of electromigration under AC and pulsed-DC stress in Cu/low-k dual damascene interconnects

An evaluation of accelerated failure time models of stress-migration and stress-induced voiding failures under vias

Diagnostic electromigration reliability evaluation with a local sensing structure

Study of a new electromigration failure mechanism by novel test structure

Constant voltage electromigration for advanced BEOL copper interconnects

Enhancement mode gallium nitride transistor reliability

Evidence for temperature-dependent buffer-induced trapping in GaN-on-silicon power transistors

Proton irradiation-induced traps causing V instabilities and RF degradation in GaN HEMTs

Trapping characteristics and parametric shifts in lateral GaN HEMTs with SiO/AlGaN gate stacks

Substrate and temperature influence on the trap density distribution in high-k III-V MOSFETs

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

Transistor aging and reliability in 14nm tri-gate technology

Systematical study of 14nm FinFET reliability: From device level stress to product HTOL

NBTI in Si cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures

NBTI in Si RMG gate stacks — Effect of high-k nitridation

Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects

A method for rapid screening of various low-k TDDB models

An investigation of dielectric thickness scaling on BEOL TDDB

On the voltage dependence of copper/low-k dielectric breakdown

An investigation of capacitance aging model for extreme low-k and high-k dielectrics

TDDB improvement of copper/dielectric in the highly-integrated BEOL structure for 28nm technology node and beyond

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology

Transistor reliability variation correlation to threshold voltage

Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies

Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI

Origins and implications of increased channel hot carrier variability in nFinFETs

Managing performance-reliability tradeoffs in multicore processors

Maximum operating voltage (V) limit for SOCs in thin form factor mobile devices with touch sensitive displays

Platform qualification methodology: Face recognition

Mitigating “No trouble found” component returns

Connecting the physical and application level towards grasping aging effects

Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies

Circuit delay variability due to wire resistance evolution under AC electromigration

Stochastic and topologically aware electromigration analysis for clock skew

Higher performance and improved reliability: Key to making photovoltaics the mainstream sustainable electricity generation source of the 21st Century

Degradation mechanisms of dye-sensitized solar cells: Light, bias and temperature effects

Stress-induced instabilities of shunt paths in high efficiency MWT solar cells

Negative bias instability in 4H-SiC MOSFETS: Evidence for structural changes in the SiC

ESD characterization of planar InGaAs devices

Improved GGSCR layout for overshoot reduction

Methodology to achieve planar technology-like ESD performance in FINFET process

A novel 8kV on-chip surge protection design in xDSL line driver IC

Characterization and reliability of III-V gate-all-around MOSFETs

Delay effects and frequency dependence of NBTI with sub-microsecond measurements

Combined trap generation and transient trap occupancy model for time evolution of NBTI during DC multi-cycle and AC stress

Self-heating and its implications on hot carrier reliability evaluations

Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET

Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices

SOI FinFET soft error upset susceptibility and analysis

Multi-cell soft errors at the 16-nm FinFET technology node

Terrestrial SER characterization for nanoscale technologies: A comparative study

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

A highly reliable DRAM 3-D wafer thinning process

Device performance analysis on 20nm technology thin wafers in a 3D package

Impact of oxide liner properties on TSV Cu pumping and TSV stress

General features of progressive breakdown in gate oxides: A compact model

Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer

On the volatility of oxide defects: Activation, deactivation, and transformation

Physical understanding of low frequency degradation of NMOS TDDB in High-k metal gate stack-based technology. Implication on lifetime assessment

New TDDB lifetime model for AC inverter-like stress in advance FinFET structure

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

Monte Carlo model of reset stochastics and failure rate estimation of read disturb mechanism in HfO RRAM

Understanding pulsed-cycling variability and endurance in HfO RRAM

A new prediction method for ReRAM data retention statistics based on 3D filament structures

A microscopic physical description of RTN current fluctuations in HfO RRAM

Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures

Impact of P/E cycling on read current fluctuation of NOR Flash memory cell: A microscopic perspective based on low frequency noise analysis

Probabilistic design for reliability in electronics and photonics: Role, significance, attributes, challenges

The electromigration behavior of copper pillars for different current directions and pillar shapes

Scenario for catastrophic failure in interconnect structures under chip package interaction

Semi-empirical stress/energy-based acceleration of temperature cycling failure

CPI reliability and EMI benefit for MIM CAP embedded C4 package

Package induced stress impact on transistor performance for ultra-thin SoC

Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues

Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology

A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients

The impact and implication of BTI/HCI decoupling on ring oscillator

Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing

SRAM Vmax stability considerations

28nm UTBB FDSOI product reliability/performance trade-off optimization through body bias operation

Product-level reliability estimator with budget-based reliability management in 20nm technology

From BTI variability to product failure rate: A technology scaling perspective

Analyzing path delays for accelerated testing of logic chips

CpK approach for the qualification of ECC-designs with single bit failures

Commercialization and reliability of 600 V GaN power switches

Thermal activation of PBTI-related stress and recovery processes in GaN MIS-HEMTs using on-wafer heaters

Origin of physical degradation in AlGaN/GaN on Si high electron mobility transistors under reverse bias stressing

Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs

Positive-bias temperature instability (PBTI) of GaN MOSFETs

Instabilities of SiC MOSFETs during use conditions and following bias temperature stress

TSV/FET proximity study using dense addressable transistor arrays

Electrical and reliability performance of atomic layer deposition HfO capping layer on porous low dielectric constant materials

The reversed intrinsic curve and voltage dependence for ultra-low k dielectrics

Effects of copper CMP and post clean process on VRDB and TDDB at 28nm and advanced technology node

A moisture-related breakdown mechanism in low-k dielectrics using a multiple I-V ramp test

Impact of process variability on BEOL TDDB lifetime model assessment

Thickness dependence on electrical and reliability properties for dense and porous low dielectric constant materials

NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes

A fWLR test structure and method for device reliability monitoring using product relevant circuits

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

Workload-dependent BTI analysis in a processor core at high level

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology

Degradation rate for surface pitting in GaN HEMT

High-voltage stress time-dependent dispersion effects in AlGaN/GaN HEMTs

Threading dislocations in III-V semiconductors: Analysis of electrical conduction

Mechanical reliability assessment of 28nm Back End of Line (BEoL) stack using finite element analysis and validation

Contact resistance of solder bump with low cost photosensitive polyimide for high performance SoC

Reliability of fine pitch COF: Influence of surface morphology and CuSn intermetallic compound formation

High voltage robustness of mold compounds under different environmental conditions

Coupled accelerated stress tests for comprehensive field reliability — Synergistic effects of moisture and temperature cycling

ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process

A novel high level ESD FDNSCR with drain side engineering in PMIC application

Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering

Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate

Understanding the underlying degradation physics for proper time-to-failure distribution selection

Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation

Mechanical and thermal stresses characterization maps on cross-sections of forward biased electronic power devices

Short localization in CPU FlipChip using thermal imaging and magnetic current imaging: Advanced fault isolation technique comparison

Employing transistor reliability testing as an FA tool for understanding HTOL product BIST failures

The impact of inverter-like transitions on device TDDB and ring oscillators

Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology

Interconnect design study for electromigration reliability improvement

Wafer-level electromigration for reliability monitoring: Quick-turn electromigration stress with correlation to package-level stress

Analysis of the SET and RESET states drift of phase-change memories by low frequency noise measurements

A collective relaxation model for resistance drift in phase change memory cells

Investigation of the data retention mechanism and modeling for the high reliability embedded split-gate MONOS flash memory

Data retention statistics and modelling in HfO resistive switching memories

RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

Cycling pattern and read/bake conditions dependence of random telegraph noise in decananometer NAND flash arrays

Conductive filaments multiplicity as a variability factor in CBRAM

Improvement of oxide reliability in NAND flash memories using tight endurance cycling with shorter idling period

SRAM stability design comprehending 14nm FinFET reliability

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

Impact of nanoscale polarization relaxation on endurance reliability of one-transistor hybrid memory using combined storage mechanisms

Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions

An investigation of process dependence of porous IMD TDDB

New insight in plasma charging impact on gate oxide breakdown in FDSOI technology

Reliability of HfAlO in multi layered gate stack

A failure physics model for hardware Trojan detection based on frequency spectrum analysis

Printed-circuit board (PCB) charge induced product yield-loss during the final test

Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag

Soft error immune latch design for 20 nm bulk CMOS

Techniques for heavy ion microbeam analysis of FPGA SER sensitivty

Analysis of advanced circuits for SET measurement

Impact of package on neutron induced single event upset in 20 nm SRAM

Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test

MBU-Calc: A compact model for Multi-Bit Upset (MBU) SER estimation

Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Hot-carrier degradation in single-layer double-gated graphene field-effect transistors

Impact of DC and RF non-conducting stress on nMOS reliability

Investigation of nitrogen enhanced NBTI effect using the universal prediction model

Comprehensive understanding of hot carrier degradation in multiple-fin SOI FinFETs

PBTI and HCI degradations of ultrathin body InGaAs-On-Insulator nMOSFETs fabricated by wafer bonding

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Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Saliva, M. Cacho, F. Ndiaye, C. Huard, V. Angot, D. Bravaix, A. Anghel, L.
Copyright Year	2015
Description	Author affiliation: TIMA, Grenoble, France (Anghel, L.) \|\| STMicroelectron., Crolles, France (Saliva, M.; Cacho, F.; Ndiaye, C.; Huard, V.; Angot, D.) \|\| IM2NP-ISEN, Maison des Technol., Toulon, France (Bravaix, A.)
Abstract	For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Next Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.
File Size	495390
File Format	PDF
ISBN	9781467373623
ISSN	19381891
DOI	10.1109/IRPS.2015.7112782
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Stress Delays Integrated circuit modeling Electric breakdown Voltage measurement MOS devices logic gates Gate Oxide Breakdown 28nm FDSOI compact model circuit level
Content Type	Text
Resource Type	Article

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