NDLI: Combined Ramp Voltage Stress and Constant Voltage Stress for optimal BTI voltage acceleration and lifetime modeling

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2015 IEEE International Reliability Physics Symposium

2014 IEEE International Reliability Physics Symposium

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Stress migration in a copper - Aluminum hybrid technology

On the distribution of stress-induced voiding failures under vias

Lifetime prediction for stress-induced voiding in nose-shape lines by using a stress-diffusion analytical model

Electromigration in strapped metal layers with large dimensions for lateral power device applications

Cross-layer system resilience at affordable power

Bias dependence of muon-induced single event upsets in 28 nm static random access memories

Heavy-ion induced single event upsets in phase-change memories

Development of thermal neutron SER-resilient high-k/metal gate technology

Toward a physical understanding of the reliability-limiting E-0.57 eV trap in GaN HEMTs

Sensitivity analysis of a technique for the extraction of interface trap density in SiC MOSFETs from subthreshold characteristics

A new method for extracting interface state and border trap densities in high-k/III-V MOSFETs

Modeling the threshold voltage instability in SiC MOSFETs at high operating temperature

I/O design optimization flow for reliability in advanced CMOS nodes

Estimation of instantaneous frequency fluctuation in a fast DVFS environment using an empirical BTI stress-relaxation model

Diagnosing bias runaway in analog/mixed signal circuits

Maximizing reliable performance of advanced CMOS circuits—A case study

New insights about oxide breakdown occurrence at circuit level

Re-investigating the adequacy of projecting ring oscillator frequency shift from device level degradation

Scaling and reliability of NAND flash devices

A new spectral approach to modeling charge trapping/detrapping in NAND Flash memories

Defects characterization of Hybrid Floating Gate/Inter-Gate Dielectric interface in Flash memory

Study on the Vt variation and bias temperature instability characteristics of TiN/W and TiN metal buried-gate transistor in DRAM application

Origin of the endurance degradation in the novel HfO-based 1T ferroelectric non-volatile memories

28nm advanced CMOS resistive RAM solution as embedded non-volatile memory

Package reliability and performance trends in an era of product integration

Mechanical stability of Cu/low-k BEOL interconnects

Effects of various assembly and reliability stresses on chip to package interaction

Acceleration of chip - Package failures in temperature cycling

A fabless company's perspective on large die Chip Package Interaction (CPI) challenges

New breakdown data generation and analytics methodology to address BEOL and mol dielectric TDDB process development and technology qualification challenges

Towards the understanding of intrinsic degradation and breakdown mechanisms of a SiOCH low-k dielectric

A new methodology for copper/low-k dielectric reliability prediction

Study on vertical TDDB degradation mechanism and its relation to lateral TDDB in Cu/low-k damascene structures

New insight in BEOL TDDB Cu diffusion mechanism: A constant current stress approach

Universality of NBTI - From devices to circuits and products

Mission Profiles derived from lifetests and field return data using inverse problem theory

Voltage Ramp Stress Test to determine TDDB performance in SRAM vehicle

Systematic reliability characterizations on Average Output Voltage (AVO) shift of Display Driver IC by HTOL

Impact of VLSI scaling on die qualification

CMOS image sensor: Process impact on dark current

SILC and gate oxide breakdown characterization of 22nm tri-gate technology

Aluminum charge/dipole passivation induced by hydrogen diffusion in high-k metal gate

Guidelines for reducing NBTI based on its correlation with effective work function studied by CV-BTI on high-k first MOS capacitors with slant-etched SiO

Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

Double-sampling architectures

Error-resilient design techniques for reliable and dependable computing

Resilient and adaptive circuits for voltage, temperature, and reliability guardband reduction

Reliability issues in GaN and SiC power devices

Impact of Cu TSVs on BEOL metal and dielectric reliability

Mass transport-induced failure in direct copper (Cu) bonding interconnects for 3-D integration

Effects of sidewall scallops on open tungsten TSVs

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Fundamentals and future applications of Laser Voltage Probing

Backside device physical analysis for yield and reliability of advanced bulk-Si CMOS ICs

A novel analysis of oxide breakdown based on dynamic observation using ultra-high speed video capturing up to 10,000,000 frames per second

Measuring propagation delays of critical paths using time-resolved LADA

Modeling of transient and static components of intrinsic emission from VLSI circuits

Energy driven modeling of OFF-state and sub-threshold degradation in scaled NMOS transistors

Origin and implications of hot carrier degradation of Gate-all-around nanowire III–V MOSFETs

Self-heating effect in FinFETs and its impact on devices reliability characterization

A unified perspective of RTN and BTI

Analyzing correlation between multiple traps in RTN characteristics

Simulation-based reliability evaluation for analog applications

Analysis of reliability/performance trade-off in Solid State Drives

Impact of sum of failure rates (SOFR) model on thermal design in SOC's for next generation game consoles

Collaborative approach for practical modeling of microcircuit failures in high-reliability applications

Novel area-efficient techniques for improving ESD performance of Drain extended transistors

Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate

Monolithic ESD protection for distributed high speed applications in 28-nm CMOS technology

Design of a low leakage ESD clamp for high voltage supply in 65nm CMOS technology

Novel dual direction PNP with self-bias ring structure

Electromigration simulation at circuit levels

Electromigration failure of circuit - like interconnects: Short length failure time distributions with active sinks and reservoirs

Interconnects exhibiting enhanced electromigration short-length effects by line width variation

Variability challenges to electromigration (EM) lifetime projections

Scaling effects on microstructure and electromigration reliability for Cu and Cu(Mn) interconnects

Dynamic off-state TDDB of ultra short channel HKMG nFETS and its implications on CMOS logic reliability

Time-dependent clustering model versus combination-based approach for BEOL/MOL and FEOL non-uniform dielectric breakdown: Similarities and disparities

Activation of electrically silent defects in the high-k gate stacks

Impact of ionic drift and vacancy defect passivation on TDDB statistics and lifetime enhancement of metal gate high-κ stacks

The physical mechanism investigation of AC TDDB behavior in advanced gate stack

Dielectric charging characterization in MEMS switches with insulator-insulator contact

Influence of temperature distribution on behavior, modeling, and reliability of BAW resonators

A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM

AAS-Maps: Aging-aware sensitivity-maps for reliability driven analog circuit design

HCI/BTI coupled model: The path for accurate and predictive reliability simulations

An LDMOS hot carrier model for circuit reliability simulation

Modeling of crystallization kinetics in phase change memories for set and read disturb regimes

Impact of electrode nature on the filament formation and variability in HfO RRAM

Impact of SET and RESET conditions on CBRAM high temperature data retention

Reset-induced variability of retention characteristics in phase change memory (PCM)

In situ biasing TEM investigation of resistive switching events in TiO-based RRAM

IRT: A modeling system for single event upset analysis that captures charge sharing effects

Impact of technology scaling on the combinational logic soft error rate

Sensitivity of NOR Flash memories to wide-energy spectrum neutrons during accelerated tests

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

Breakdown mechanisms in MgO based magnetic tunnel junctions and correlation with low frequency noise

Suitability of high-k gate oxides for III–V devices: A PBTI study in InAs devices with Al

SiGe composition and thickness effects on NBTI in replacement metal gate / high-κ technologies

A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

Correlation of BTI induced device parameter degradation and variation in scaled Metal Gate / High-k CMOS technologies

Circuit speed timing jitter increase in random logic operation after NBTI stress

Fast characterization of PBTI and NBTI induced frequency shifts under a realistic recovery bias using a ring oscillator based circuit

The impact of Hot Carrier Injection (HCI) on Voltage Control Oscillator lifetime prediction

Adaptive Wearout Management with in-situ aging monitors

Fast aging degradation rate prediction during production test

Correlating reliability to yield for liftoff metallization

Threshold voltage instabilities in D-mode GaN HEMTs for power switching applications

Enhancement of V drift for repetitive gate stress pulses due to charge feedback effect in GaN MIS-HEMTs

Threshold voltage drift (PBTI) in GaN D-MODE MISHEMTs: Characterization of fast trapping components

Current collapse in GaN heterojunction field effect transistors for high-voltage switching applications

Role of buffer doping and pre-existing trap states in the current collapse and degradation of AlGaN/GaN HEMTs

Electrical breakdown in polymers for BEOL applications: Dielectric heating and humidity effects

Tunneling currents and reliability of atomic-layer-deposited SiBCN for low-κ spacer dielectrics

TDDB at low voltages: An electrochemical perspective

Low-field TDDB reliability data to enable accurate lifetime predictions

Effect of line-overlay and via-misalignment on dielectric reliability for different patterning schemes

DC / AC BTI variability of SRAM circuits simulated using a physics-based compact model

On-chip aging compensation for output driver

Universal NBTI model and its application for high frequency circuit simulation

Scaling of BTI reliability in presence of time-zero variability

A reliability lab-on-chip using programmable arrays

A physical and scalable aging model for digital library characterization

System-level modeling of microprocessor reliability degradation due to BTI and HCI

The impact of high V drifts tail and real workloads on SRAM reliability

Trap-related parametric shifts under DC bias and switched operation life stress in power AlGaN/GaN HEMTs

(CD-5) TDDB breakdown of th-SiO on 4H-SiC: 3D SEM failure analysis

Electrical characterization and reliability analysis of Al/AlGaN/GaN MISH structure

High-voltage double-pulsed measurement system for GaN-based power HEMTs

On the prediction of optimal baking schedules in plastic SMD microelectronic devices

Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS

Evaluation of geometry layout and metal pattern to optimize ESD performance of silicon controlled rectifier (SCR)

Lower trigger voltage design for ESD protection device applied in PMIC application

A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

Study on ESD protection design with stacked low-voltage devices for high-voltage applications

New methodology for drift analysis on reliability trial

Component and system effective lifetime & FIT model in advanced technology

Is your silicon reliable? A system approach of silicon qualification methodology

N-contacts degradation analysis of white flip chip LEDs during reliability tests

Imaging and nanoprobing of graphene layers on Ni damascene interconnects by conductive atomic force microscopy

Time resolved emission observation from top surface in avalanche breakdown of power MOSFET

Adaptive grinding and polishing of packaged integrated circuits

Demonstrating individual leakage path from random telegraph signal of stress induced leakage current

A single device based voltage step stress (VSS) technique for fast reliability screening

Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs

Defect density evaluation in a high-k MOSFET gate stack combining experimental and modeling methods

Voltage pulse stress effect on gate stack TDDB distributions at nanometric scale: Consequence on aging by ESD

Frequency dependence of TDDB & PBTI with OTF monitoring methodology in high-k/metal gate stacks

Mechanism exploration on Cu interconnect negative resistance shift during stress migration

Electromigration analysis of full-chip integrated circuits with hydrostatic stress

Investigation of vacancy diffusion path for stress migration failure mode in highly scaled Cu/low-k interconnects

Reliability performance of different layouts of wide metal tracks

Model based method for electro-migration stress determination in interconnects

Effect of via arrangement on electromigration performance

Stacked-etch induced charge loss in Hybrid Floating Gate cells using high-κ Inter-Gate Dielectric

Investigation of random telegraph noise amplitudes in hafnium oxide resistive memory devices

Write disturb analyses on half-selected cells of cross-point RRAM arrays

Voltage-dependent random telegraph noise (RTN) in HfO resistive RAM

Instability of HfO RRAM devices: Comparing RTN and cycling variability

Bit error rate analysis in Charge Trapping memories for SSD applications

Reliability investigation of T-RAM cells for DRAM applications

Stochastic failure model for endurance degradation in vacancy modulated HfO RRAM using the percolation cell framework

Energy control paradigm for compliance-free reliable operation of RRAM

New circuit model for investigating plasma damage in FDSOI devices

Defect formation in III–V fin grown by aspect ratio trapping technique: A first-principles study

Effect of I/O oxide process optimization on the nbti dependence of T scaling for a 20 nm bulk planar Replacement Gate process

System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

Using thermal cycle and temperature / voltage testing to reduce the incidence of resistive / open reliability defects

Set level at speed HTOL test for reliability qualification of high speed mobile applications

Analysis of the reliability impact on high-k metal gate SRAM with assist-circuit

Setting use conditions for reliability modeling

65 nm fault tolerant latch architecture based on transient propagation blocking

Impact of body bias on soft error tolerance of bulk and Silicon on Thin BOX structure in 65-nm process

Preventing single event latchup with deep P-well on P-substrate

Utilizing device stacking for area efficient hardened SOI flip-flop designs

Soft error rate comparison of various hardened and non-hardened flip-flops at 28-nm node

SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts

Similarity and difference in temperature dependent recovery of HCS and NBTI

BTI recovery in 22nm tri-gate technology

Frequency dependence of NBTI in high-k/metal-gate technology

Gate bias temperature stress-induced off-state leakage in nMOSFETs: Mechanism, lifetime model and circuit design consideration

The effects of biaxially-tensile strain to properties of Si/SiO interface states generated by electrical stress

Process dependence of AC/DC PBTI in HKMG n-MOSFETs

Combined Ramp Voltage Stress and Constant Voltage Stress for optimal BTI voltage acceleration and lifetime modeling

Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes

On electron-trap transformation and its unexpected frequency dependence under dynamic positive-bias temperature stressing

Comprehensive study of NBTI under compressive and tensile strain

Energy-driven Hot-Carrier model in advanced nodes

A reliable method for the extraction of the lateral position of defects in ultra-scaled MOSFETs

A new efficient method for characterizing time constants of switching oxide traps

Hot-carrier induced dielectric breakdown (HCIDB) challenges of a new high performance LDMOS generation

Physical modeling of hot-carrier degradation for short- and long-channel MOSFETs

New observations on the random telegraph noise induced Vth variation in nano-scale MOSFETs

A single-trap study of PBTI in SiON nMOS transistors: Similarities and differences to the NBTI/pMOS case

Mechanical stress effects on p-channel MOSFET performance and NBTI reliability

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Combined Ramp Voltage Stress and Constant Voltage Stress for optimal BTI voltage acceleration and lifetime modeling

Content Provider	IEEE Xplore Digital Library
Author	Linder, B.P. Ando, T.
Copyright Year	2014
Description	Author affiliation: T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA (Linder, B.P.; Ando, T.)
Abstract	Bias temperature instability (BTI) is the primary reliability mechanism limiting further thinning of the dielectric with future CMOS scaling [1]. This has led to an increased emphasis on quick screening of different processes using Ramp Voltage Stress (RVS) [2], while Constant Voltage Stress (CVS) is typically utilized for more in depth modeling and lifetime projection. This strategy, though, severely underutilizes RVS and does not optimally combine the strengths of each test. Because the voltage is ramped during an RVS stress, a derivative of the RVS trace vs. ramp voltage yields an extremely detailed understanding of the voltage dependence of BTI. On the other hand, CVS directly measures the time evolution of BTI. This paper highlights the pitfalls of relying on just CVS for BTI lifetime projections and also demonstrates the complimentary nature of RVS and CVS for lifetime extraction. In addition, this paper will detail the tremendous benefit of a slow ramp RVS test, with ramp rates as low as 100 μV/s, for BTI modeling and lifetime extrapolation down to use conditions.
File Size	254225
File Format	PDF
ISBN	9781479933174
ISSN	19381891
DOI	10.1109/IRPS.2014.6861185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Acceleration Time measurement Logic gates Mathematical model Low voltage NBTI Semiconductor device reliability High-K gate dielectric Accelerated aging PBTI
Content Type	Text
Resource Type	Article

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