NDLI: Failure Analysis of Surface Inversion

Content Provider	IEEE Xplore Digital Library
Author	Schroen, Walter
Copyright Year	1973
Description	Author affiliation: Texas Instruments Incorporated, Dallas, Texas (Schroen, Walter)
Abstract	This paper is intended to give some guidance for a workshop session on surface inversion. It first highlights the key causes of surface inversion, such as electronic and ionic charges, surface and bulk contamination, and leakage mechanisms. Second, the paper describes a number of widely used failure analysis techniques which permit the study of surface inversion and accumulation in MOS and bipolar devices and circuits. These techniques include the evaluation of test structure data, as gained by capacitor and field plate arrangements at variable temperatures, and the analysis of actual circuits using the scanning electron microscope, the photoresponse scanner, the microprobe, and electrical characterization. As examples for surface inversion, temperature-voltage inversion, surface and bulk generated currents, and lateral charge spreading are described. Some final comments lead to the more encompassing subject of device parameter stability improvement by process control.
Starting Page	117
Ending Page	123
File Size	9227366
Page Count	7
File Format	PDF
ISSN	07350791
DOI	10.1109/IRPS.1973.362581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1973-04-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Failure analysis Surface contamination Circuit testing Scanning electron microscopy Voltage Substrates Instruments MOS capacitors Temperature Circuit stability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices

Efficient Computer-Aided Failure Analysis of Integrated Circuits using Scanning Electron Microscopy

Failure Analysis Applications of the Scanning Electron Microscope

Temperature Dependence of the Hard Breakdown Current of MOS Capacitors

Electrical failure of multilayer ceramic capacitors subjected to environmental screening testing

A new paradigm of using TEM in yield enhancement failure analysis for sub-micron integrated circuit devices

An accurate discrimination method of gate oxide breakdown positions by a new test structure of MOS capacitors

Failure Analysis using a Scanning Electron Microscope

Couple passive voltage contrast with scanning probe microscope to identify invisible defect out

Failure Analysis of Surface Inversion

Similar Documents

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices

Efficient Computer-Aided Failure Analysis of Integrated Circuits using Scanning Electron Microscopy

Failure Analysis Applications of the Scanning Electron Microscope

Temperature Dependence of the Hard Breakdown Current of MOS Capacitors

Electrical failure of multilayer ceramic capacitors subjected to environmental screening testing

A new paradigm of using TEM in yield enhancement failure analysis for sub-micron integrated circuit devices

An accurate discrimination method of gate oxide breakdown positions by a new test structure of MOS capacitors

Failure Analysis using a Scanning Electron Microscope

Couple passive voltage contrast with scanning probe microscope to identify invisible defect out

Failure Analysis of Surface Inversion