NDLI: A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Koike, N. Tatsuuma, K.
Copyright Year	2002
Description	Author affiliation: ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan (Koike, N.; Tatsuuma, K.)
Abstract	A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as /spl tau/(I/sub d//W)/sup 2//spl prop/(I/sub sub//I/sub d/)/sup -m/. The formula is different from the conventional /spl tau/I/sub d//W-I/sub sub//I/sub d/ model in that the exponent of I/sub d//W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical /spl tau/-I/sub sub//W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low energy carriers to create the damage.
Sponsorship	IEEE Electron Devices Soc. IEEE Reliability Soc
Starting Page	86
Ending Page	92
File Size	512225
Page Count	7
File Format	PDF
ISBN	0780373529
DOI	10.1109/RELPHY.2002.996614
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hot carriers Degradation MOSFET circuits Voltage Electron traps Drain avalanche hot carrier injection Spontaneous emission Radiative recombination Charge carrier processes Circuit simulation
Content Type	Text
Resource Type	Article

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