NDLI: Triggers, data flow and the synchronization between the Auger surface detector and the AMIGA underground muon counters

Content Provider	IEEE Xplore Digital Library
Author	Szadkowski, Z.
Copyright Year	2010
Description	Author affiliation: University of Łódź, Department of Physics and Applied Informatics, 90-236, Poland (Szadkowski, Z.)
Abstract	The aim of the AMIGA project (Auger Muons and Infill for the Ground Array) is an investigation of Extensive Air Showers at energies lower than by standard Auger array, where the transition from galactic to extragalactic sources is expected. The Auger array is enlarged by a relatively small dedicated area of surface detectors with nearby buried underground muon counters at half or less the standard 1.5 km grid. Lowering the Auger energy threshold by more than one order of magnitude allows a precise measurement of the cosmic ray spectrum in the very interesting regions of the second knee and the ankle. The paper describes the working principle of the Master/Slave (standard Auger surface detector/the underground muon counters) synchronous data acquisition, general triggering and the extraction of data corresponding to the real events from underground storage buffers applied in two prototypes: A) with 12.5 ns resolution (80 MHz) built from 4 segments: standard Auger Front End Board (FEB) and Surface Single Board Computer (SSBC) (on the surface) and the Digital Board with the FPGA and the Microcontroller Board (underground), B) with 4-times higher: 3.125 ns resolution (320 MHz) built with two segments only: new surface Front End Board supported by the $NIOS^{®}$ processor and CycloneIII™ Starter Kit board underground, working also with $NIOS^{®}$ virtual processor, which replaces the external TI µC, which in meantime became obsolete. The system with the $NIOS^{®}$ processors can remotely modify and update: the AHDL firmware creating the hardware FPGA net structure responsible for the fast DAQ, the internal structure of the $NIOS^{®}$ (resources and peripherals) and the $NIOS^{®}$ firmware (C code) responsible for software data management. With the standard µC, the µC firmware was fixed and could not be updated remotely. The 80 MHz prototype passed laboratory tests with real scintillators. The 320 MHz prototype (still being optimized) is considered as the ultimate AMIGA design.
Starting Page	1
Ending Page	8
File Size	2438451
Page Count	8
File Format	PDF
ISBN	9781424471089
e-ISBN	9781424471102
DOI	10.1109/RTC.2010.5750413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Detectors Radiation detectors Mesons Clocks Random access memory Synchronization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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