NDLI: A large-scale FPGA-based trigger and dead-time free DAQ system for the KAOS spectrometer at MAMI

Content Provider	IEEE Xplore Digital Library
Author	Achenbach, P.
Copyright Year	2010
Description	Author affiliation: Institut für Kernphysik, Johannes Gutenberg-Universität, D-55099 Mainz, Germany (Achenbach, P.)
Abstract	The KAOS spectrometer is maintained by the A1 collaboration at the Mainz Microtron MAMI with a focus on the study of (e, $e′K^{+})$ coincidence reactions. For its electron-arm two vertical planes of fiber arrays, each comprising approximately 10 000 fibers, are operated close to zero degree scattering angle and in close proximity to the electron beam. A nearly dead-time free DAQ system to acquire timing and tracking information has been installed for this spectrometer arm. The signals of 144 multi-anode photomultipliers are collected by 96-channel front-end boards, digitized by double-threshold discriminators and the signal time is picked up by state-of-the-art F1 time-to-digital converter chips. In order to minimize background rates a sophisticated trigger logic was implemented in newly developed VUPROM modules. The trigger performs noise suppression, signal cluster finding, particle tracking, and coincidence timing, and can be expanded for kinematical matching $(e′K^{+})$ coincidences. The full system was designed to process more than 4 000 read-out channels and to cope with the high electron flux in the spectrometer and the high count rate requirement of the detectors. It was successfully in-beam tested at MAMI in 2009.
Starting Page	1
Ending Page	7
File Size	2169765
Page Count	7
File Format	PDF
ISBN	9781424471089
e-ISBN	9781424471102
DOI	10.1109/RTC.2010.5750412
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Logic gates Data acquisition Field programmable gate arrays Connectors Digital signal processing Electron beams
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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