NDLI: A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS

Content Provider	IEEE Xplore Digital Library
Author	Tretter, G. Khafaji, M. Fritsche, D. Carta, C. Ellinger, F.
Copyright Year	2015
Description	Author affiliation: Circuit Design & Network Theor., Tech. Univ. Dresden, Dresden, Germany (Tretter, G.; Khafaji, M.; Fritsche, D.; Carta, C.; Ellinger, F.)
Abstract	This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.
Starting Page	347
Ending Page	350
File Size	477285
Page Count	4
File Format	PDF
e-ISBN	9781479976423
DOI	10.1109/RFIC.2015.7337776
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Clocks CMOS technology Bandwidth Silicon germanium Transmission line measurements Ash single-core Analog-to-digital converter (ADC) flash ADC non-time-interleaved
Content Type	Text
Resource Type	Article

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