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A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS
| Content Provider | MDPI |
|---|---|
| Author | Luan, Jian Zheng, Xuqiang Wu, Danyu Zhang, Yuzhen Wu, Linzhen Zhou, Lei Wu, Jin Liu, Xinyu |
| Copyright Year | 2022 |
| Description | This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 $mm^{2}$ and consumes 432 mW power consumption. |
| Starting Page | 688 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics11050688 |
| Journal | Electronics |
| Issue Number | 5 |
| Volume Number | 11 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-02-23 |
| Access Restriction | Open |
| Subject Keyword | Electronics Imaging Science Analog-to-digital Converter (adc) Time-interleaved (ti) Cmos Real-time Output Dedicated Calibration Deterministic Latency |
| Content Type | Text |
| Resource Type | Article |
