NDLI: A 5 Gbps low noise receiver in 0.13µm CMOS for wireless optical communications

Content Provider	IEEE Xplore Digital Library
Author	Nakhkoob, B. Hella, M.M.
Copyright Year	2012
Description	Author affiliation: ECSE Department, Rensselaer Polytechnic Institute, Troy, NY 12180, USA (Nakhkoob, B.; Hella, M.M.)
Abstract	A wideband, high gain, and low noise optical receiver targeting imaging architectures for optical wireless communications is presented. For line of sight tracking in optical wireless communications, a switching matrix is employed between the pixel/photodetctor array and the transimpedance amplifier. The optical receiver consists of a low noise wideband TIA, where noise and stability are optimized in the presence of the switch, using a series inductor at the input. The TIA is followed by a limiter with offset cancellation and 50 Ω output buffer capable of 900 mv p-p differential output swing over the 50 Ω resistance of measurement equipment. The receiver implemented in IBM 130nm CMOS technology achieves a bit error rate of $10^{−12}$ at 5 Gbps corresponding to 2.8 µA current at the input, in presence of 1 pF input capacitance representing the photodiode. The total power consumption including the on chip 50 Ω differential output buffer is 68 mW from 1.5V DC supply, while the die area including bonding pads and output buffer is 1106 × 895 $µm^{2}.$
Starting Page	327
Ending Page	330
File Size	1635485
Page Count	4
File Format	PDF
ISBN	9781467304139
ISSN	15292517
e-ISBN	9781467304160
e-ISBN	9781467304153
DOI	10.1109/RFIC.2012.6242292
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-17
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Optical switches Optical receivers Resistors Bandwidth Lownoise amplifiers CMOS image sensors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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