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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Weldon, T.P. Lieu, D.T. Davis, M.J. |
| Copyright Year | 2005 |
| Description | Author affiliation: North Carolina Univ., Charlotte, NC, USA (Weldon, T.P.; Lieu, D.T.; Davis, M.J.) |
| Abstract | A simple circuit consisting of an nMOS transistor in parallel with a pMOS transistor is shown to reduce nonlinear distortion. Measured experimental results show more than 10 dB reduction in third order distortion at 1 GHz for a prototype 0.18 micron CMOS integrated circuit. Experimental data further suggest that the relative increase in the third order output intercept point greatly exceeds the corresponding increase in power supply current. Since the proposed circuit is itself a three-terminal device, it can also be used as a building block for larger circuits. Finally, theoretical linearization conditions are presented in terms of the gains and intercept points of the nMOS and pMOS devices. |
| Sponsorship | IEEE Microwave Theory and Techniques Soc. IEEE Electron Devices Soc. IEEE Solid State Circuits Soc |
| Starting Page | 233 |
| Ending Page | 236 |
| File Size | 716646 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780389832 |
| ISSN | 15292517 |
| DOI | 10.1109/RFIC.2005.1489641 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-06-12 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MOSFETs Nonlinear distortion Circuit topology Couplers MOS devices Integrated circuit measurements Prototypes CMOS integrated circuits Frequency Welding |
| Content Type | Text |
| Resource Type | Article |
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