NDLI: Automatic synthesis of a 2.1 GHz SiGe low noise amplifier

Content Provider	IEEE Xplore Digital Library
Author	Gang Zhang Dengi, A. Carley, L.R.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Gang Zhang)
Abstract	A 2.1 GHz low noise amplifier in a 0.5 /spl mu/m 47 GHz SiGe BiCMOS process was synthesized and sent to fabrication. The circuit was synthesized to simultaneously meet multiple design specifications Including noise figure, gain, power, impedance match, intermodulation, compression, stability with a state-of-art simulation-based circuit synthesis tool. The synthesis setup took about two days, and the synthesis run took about 2 hours on a pool of 10 networked SUN workstations. Noise figure of 1.2 dB, power gain of 16 dB, IIP3 of -6 dB, S11 of less than -15 dB, were achieved with 3.7 mA bias current at 2.5 V power supply. Data generated during synthesis was processed to show design trade-offs among competing performance goals. The trade-off between optimum noise match and input impedance match Is discussed.
Sponsorship	IEEE Microwave Theory and Techniques Soc. IEEE Electron Devices Soc. IEEE Solid States Circuits Soc
Starting Page	125
Ending Page	128
File Size	369191
Page Count	4
File Format	PDF
ISBN	0780372468
ISSN	15292517
DOI	10.1109/RFIC.2002.1011938
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon germanium Germanium silicon alloys Low-noise amplifiers Circuit synthesis Network synthesis Circuit noise Noise figure Impedance matching BiCMOS integrated circuits Fabrication
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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