NDLI: Development of secondary breakdown circuit for DV/DT analysis of SIC devices

Content Provider	IEEE Xplore Digital Library
Author	Schrock, J.A. Ray, W.B. Bilbao, A.V. Kelley, M.D. Hirsch, E.A. Holt, S.L. Bayne, S.B.
Copyright Year	2015
Description	Author affiliation: Center for Pulsed Power & Power Electron., Texas Tech Univ., Lubbock, TX, USA (Schrock, J.A.; Ray, W.B.; Bilbao, A.V.; Kelley, M.D.; Hirsch, E.A.; Holt, S.L.; Bayne, S.B.)
Abstract	Silicon carbide (4H-SiC) is a leading option for increasing the power density of pulsed power and power electronic systems1, 2. SiC devices used in high voltage switching applications experience high dV/dt due to fast switching transients. Under high dV/dt conditions the devices can exhibit spurious turn-ON. For SiC devices to achieve widespread acceptance the dV/dt limit must be established. To measure the dV/dt limit, a circuit comprised of four silicon avalanche BJTs operating in secondary breakdown was constructed. This circuit is capable of generating dV/dts well in excess of what SiC unipolar and bipolar devices might be exposed to in typical applications. Two SiC diodes in an “OR” configuration are used to perform a comprehensive dV/dt analysis as a function of dc bias. Using this experimental setup dV/dts up to 200 V/ns were applied to SiC MOSFETs, and the induced gate to source voltage was measured. Preliminary dV/dt results achieved with the secondary breakdown circuit are shown for a range of dc biases.
Starting Page	1
Ending Page	5
File Size	778722
Page Count	5
File Format	PDF
e-ISBN	9781479984039
DOI	10.1109/PPC.2015.7296921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon carbide DVD MOSFET Logic gates Power electronics Electric breakdown Voltage measurement
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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