NDLI: Improving the gate oxide integrity of very high voltage MCT and IGBT devices by external gettering of metal impurities

Content Provider	IEEE Xplore Digital Library
Author	Herr, E. Baltes, H. Thiemann, U. Stockmeier, T.
Copyright Year	1994
Description	Author affiliation: Phys. Electron. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland (Herr, E.)
Abstract	We observed that gate oxides of MCT and IGBT devices exhibited lower breakdown field strengths when the devices were fabricated on float-zone (FZ) instead of Czochralski-grown (CZ) silicon starting material. This is because of the different precipitation behavior of heavy metal contaminants. Using neutron activation analysis (NAA), we determined Fe and Ni concentration levels that weaken the gate oxides of BiMOS devices on FZ silicon. We compared the effect of various external gettering techniques on the gate oxide integrity. External gettering by polysilicon layers and by argon implantation damage were employed on the wafer back to improve the gate oxide integrity of BiMOS devices fabricated on FZ material.
Starting Page	213
Ending Page	218
File Size	721359
Page Count	6
File Format	PDF
ISBN	0780314948
ISSN	10636854
DOI	10.1109/ISPSD.1994.583725
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-31
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulated gate bipolar transistors Gettering Silicon Breakdown voltage Thyristors Iron MOSFETs Neutrons Activation analysis Argon
Content Type	Text
Resource Type	Article

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Improving the gate oxide integrity of very high voltage MCT and IGBT devices by external gettering of metal impurities