NDLI: Designing Testable Plas for both Offline Testing and Concurrent Error Detection

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IEEE Technical Conference on Southern Tier

Proceedings of the IEEE Southern Tier Technical Conference

Proceedings of the 1987 IEEE Southern Tier Technical Conference, 1987.

Innovative Helical Wrap Installation of Fiber Optic Cable

The Nesc, Probability, Reliability and the Future

Utility Application of Static Var-Compensation

Designing Testable Plas for both Offline Testing and Concurrent Error Detection

A Simplified Self-Checking Design of Multioutput Circuits

Quasi-universal VLSI multiplier with signed digit arithmetic

Multiplier Design Using Signed-Digit Number System

Direct Computation of the Polynomial Expression Ax/sup 2/ + Bx + C

Innovative Variable Mesh Simulator

Gummel-Poon Model Parameter Optimization for a Power Transistor

A Generalized Approach for Automatic Test Pattern Generation

Programmable Placement Pressure in a Placement Head for Surface Mounted Devices

Fatigue and Creep in Solder Joints

Optical Detection of Rent Pins in a High-Density Array

Locating Signal Line Defects with Thermal Image Analysis

Variable end-of-travel Sensor

On the Stability Analysis of an Adaptive Control System with a Simplified Control Procedure

On the Optimal Pulse Control of an Electric Drive

Image Recognition Procedure in an Adaptive Control System Applied to a Robotic Manipulator

Voice Recognition - the Next Generation Man-Machine Input Device?

A Computer Controlled Aircraft Defense System (CCADS)

A Practical Reliability Evaluation of Embedded Avionic Software

Communicating with Your Customers Determining Their Needs

Binary Image Transforms: An old twist in Image Processing revisited

Low-cost Microcomputer Networking: Some Practical Considerations

The MAP Pilot Project at IBM Endicott

Speech Recognition: A TutoriaI on the Subject

Engineering Problem Analysis with Microcomputer Spreadsheets

Computer machine contol language development

Software Development - from Concept to Completion

On the Optimization of Search Heuristics: A Fuzzy Approach

Innovative Helical Wrap Installation of Fiber Optic Cable

The Nesc, Probability, Reliability and the Future

Utility Application of Static Var Compensation

Designing Testable Plas for both Offline Testing and Concurrent Error Detection

Quasi-Universal VLSI Multiplier with Signed Digit Arithmetic

Multiplier Design Using Signed-digit Number System

Direct Computation of the Polynomial Expression Ax/sup 2/ + Bx + C

Innovative Variable Mesh Simulator

Gummel-Poon Model Parameter Optimization for a Power Transistor

A Generalized Approach for Automatic Test Pattern Generation

Programmable Placement Pressure in a Placement Head for Surface Mounted Devices

Fatigue and Creep in Solder Joints

Optical Detection of Bent Pins in a High-Density Array

Locating Signal Line Defects with Thermal Image Analysis

Variable End-of-Travel Sensor

On the Stability Analysis of an Adaptive Control System with a Simplified Control Procedure

On the Optimal Pulse Control of an Electric Drive

Image Recognition Procedure in an Adaptive Control System Applied to a Robotic Manipulator

Voice Recognition - The Next Generation Man-Machine, Input Device?

A Computer Controlled Aircraft Defense System (CCADS)

a Practical Reliability Evaluation of Embedded Avionic Software

Communicating with Your Customers Determining Their Needs

Binary Image Transforms: An old twist in Image Processing revisited

Low-Cost Microcomputer Networking: Some Practical Considerations

The MAP Pilot Project at IBM Endicott

Speech Recognition: A Tutorial on the Subject

Engineering Problem Analysis with Microcomputer Spreadsheets

Computer Machine Control Language Development

Software Development -- from Concept to Completion

On the Optimization of Search Heuristics: a Fuzzy Approach

A Simplified Self-Checking Design of Multioutput Circuits

Designing Testable Plas for both Offline Testing and Concurrent Error Detection

Content Provider	IEEE Xplore Digital Library
Author	Sharma, R. Rajashekhara, T.N.
Copyright Year	1987
Description	Author affiliation: Dept. of Electrical & Computer Engineering, University of Wisconsin (Sharma, R.)
Abstract	In this paper, we present an improved design of testable PLAs for offline testing and suggest a unified approach for both offline testing and Concurrent Error Detection (CED). This design offers a more efficient use of the additional hardware required for designing testable PLAs. The additional hardware required includes an address decoder [1] to select or deselect the product lines of the PLA, a ripple counter to generate the address for the decoder, and a Totally Self Checking (TSC) checker for the output lines of the PLA. The design requires only two additional pinouts on the chip in contrast to (1og/sub 2/(m+l), + 1) additional pinouts [1], where m is the number of product lines in the PLA. The additional hardware used for CED is also effectively utilized during offline testing, and the design is suitable for built-in testing of PLAs. The test procedures cover all single mode stuck-at, bridging, and crosspoint faults.
Starting Page	64
Ending Page	68
File Size	363808
Page Count	5
File Format	PDF
DOI	10.1109/STIER.1987.716381
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-04-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Programmable logic arrays Decoding Fault detection Hardware Clocks
Content Type	Text
Resource Type	Article

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