NDLI: Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories

Content Provider	IEEE Xplore Digital Library
Author	Maconi, A. Compagnoni, C.M. Amoroso, S.M. Mascellino, E. Ghidotti, M. Padovini, G. Spinelli, A.S. Lacaita, A.L. Mauri, A. Ghidini, G. Galbiati, N. Sebastiani, A. Scozzari, C. Greco, E. Camozzi, E. Tessariol, P.
Copyright Year	2010
Description	Author affiliation: Numonyx, R&D-Technology Development, 20041 Agrate Brianza (MI), Italy (Mauri, A.; Ghidini, G.; Galbiati, N.; Sebastiani, A.; Scozzari, C.; Greco, E.; Camozzi, E.; Tessariol, P.) \|\| Dipartimento di Elettronica e Informazione, Politecnico di Milano-IU.NET, 20133, Italy (Maconi, A.; Compagnoni, C.M.; Amoroso, S.M.; Mascellino, E.; Ghidotti, M.; Padovini, G.; Spinelli, A.S.; Lacaita, A.L.)
Abstract	This paper presents a detailed investigation of the ISPP dynamics of charge-trap memory capacitors, considering not only the flat-band voltage but also the bottom oxide electric field and tunneling current evolution during programming. Differently from the floating-gate case, results on nitride-based memories show that the flat-band increase per step does not equal the step amplitude of the gate staircase, decreasing, moreover, as programming proceeds. As a consequence, the electric field and tunneling current through the bottom oxide are shown to largely increase. Using results at different temperatures and on samples with different stack compositions, this dynamics is explained in terms of a drop of the programming efficiency as more and more charge is stored in the nitride layer, due to the reduction of the number of free traps available for capturing the injected electrons.
Starting Page	444
Ending Page	447
File Size	366914
Page Count	4
File Format	PDF
ISBN	9781424466580
ISSN	19308876
e-ISBN	9781424466610
DOI	10.1109/ESSDERC.2010.5618183
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-14
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programming SONOS devices Transient analysis Electron traps Capacitors Logic gates programming efficiency Charge trap memories SONOS memories TANOS memories incremental step pulse programming
Content Type	Text
Resource Type	Article

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