NDLI: A New Analytical Model of CMOS Latch-up

Content Provider	IEEE Xplore Digital Library
Author	Leroux, C. Gautier, J. Chante, J.P.
Copyright Year	1989
Description	Author affiliation: D. LETI,CENG, 85X av. des Martyrs, 38041 Grenoble Cédex (Leroux, C.; Gautier, J.) \|\| LPCA, INSA, 20 av. Albert Einstein, 69621 Villeurbanne Cédex (Chante, J.P.)
Abstract	Classical analytical models of CMOS latch-up assume that the latch-up phenomenon is the result of the interaction of two or more bipolar transistors. With such a model, sustaining of latch-up can be only explained by a sufficiently high value for the product of bipolar gains (classically ßn·ßp¿1 or ßn·ßp¿ f (Iddmax) [1]). Such an explanation fails with the reduction of gain at high injection current levels [2]. We can also ask, whether we can even speak of bipolar transistors when the base-collector junctions have disappeared. This effect can be observed in figure 1[3]. Our model of latch-up includes a novel, four terminal, bipolar transistor model. With it we can explain the sustaining of latch-up at high injection levels, voltage drops through the base can be accounted for, and the disappearance of the base-collector junction can be represented. Our model is compared with experimental results, and good correlation was seen between measured and simulated values of holding voltage.
Starting Page	423
Ending Page	426
File Size	1026314
Page Count	4
File Format	PDF
ISBN	0387510001
DOI	10.1007/978-3-642-52314-4_86
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-09-11
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Springer-Verlag Heidelberg
Subject Keyword	Analytical models Semiconductor process modeling Bipolar transistors Voltage Semiconductor device modeling CMOS technology Resistors Substrates Transmission line theory Equations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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