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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lerme, M. Arena, C. Deleonibus, S. Demolliens, O. Fayolle, M. Gobil, Y. Guegan, G. Heitzmann, M. Laurens, M. Martin, F. Morand, Y. Molle, P. Vinet, F. |
| Copyright Year | 1994 |
| Description | Author affiliation: GRESSI-LETI (CEA-Technologies Avancées) DMEL-CENG, 17 rue des Martyrs 38054 Grenoble Cedex 9 France (Lerme, M.; Arena, C.; Deleonibus, S.; Demolliens, O.; Fayolle, M.; Gobil, Y.; Guegan, G.; Heitzmann, M.; Martin, F.; Molle, P.; Vinet, F.) || SGS-THOMSON Microelectronics-Centre de Crolles 38920 Crolles France (Laurens, M.) || SGS-THOMSON Microelectronics-Centre de Grenoble, GRESSI-LETI (CEA-Technologies Avancées) DMEL-CENG, 17 rue des Martyrs 38054 Grenoble Cedex 9 France (Morand, Y.) |
| Abstract | Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate that this CMP technique is compatible with a 0.35 CMOS technology in terms of transistor behaviour and triple metal process assembly. |
| Starting Page | 121 |
| Ending Page | 124 |
| File Size | 1415503 |
| Page Count | 4 |
| File Format | |
| ISBN | 0863321579 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-09-11 |
| Publisher Place | Scotland |
| Access Restriction | Subscribed |
| Rights Holder | Editions Frontieres |
| Subject Keyword | CMOS technology Chemical technology Planarization Metallization Dielectrics Sputter etching MOSFETs Sputtering Tin CMOS process |
| Content Type | Text |
| Resource Type | Article |
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